////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.
////////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor: Xilinx
// \   \   \/     Version: P.15xf
//  \   \         Application: netgen
//  /   /         Filename: MEM_RD_DUAL_map.v
// /___/   /\     Timestamp: Wed Dec 05 22:42:58 2012
// \   \  /  \ 
//  \___\/\___\
//             
// Command	: -intstyle ise -s 2 -pcf MEM_RD_DUAL.pcf -sdf_anno true -sdf_path netgen/map -insert_glbl true -w -dir netgen/map -ofmt verilog -sim MEM_RD_DUAL_map.ncd MEM_RD_DUAL_map.v 
// Device	: 5vlx20tff323-2 (PRODUCTION 1.73 2012-04-23)
// Input file	: MEM_RD_DUAL_map.ncd
// Output file	: D:\Workspace\xilinx workspace\HFM_DETECTOR\netgen\map\MEM_RD_DUAL_map.v
// # of Modules	: 1
// Design Name	: MEM_RD_DUAL
// Xilinx        : D:\Xilinx\14.1\ISE_DS\ISE\
//             
// Purpose:    
//     This verilog netlist is a verification model and uses simulation 
//     primitives which may not represent the true implementation of the 
//     device, however the netlist is functionally correct and should not 
//     be modified. This file cannot be synthesized and should only be used 
//     with supported simulation tools.
//             
// Reference:  
//     Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//             
////////////////////////////////////////////////////////////////////////////////

`timescale 1 ns/1 ps

module MEM_RD_DUAL (
  clk, rst, ch2_rd_i, ch2_rd_r, addr_rd_ch1, addr_rd_ch2, ch1_rd_i, ch1_rd_r, addr_wr, ch2_to_rd_i, ch1_to_rd_i, ch2_to_rd_r, ch1_to_rd_r
);
  input clk;
  input rst;
  output [15 : 0] ch2_rd_i;
  output [15 : 0] ch2_rd_r;
  output [8 : 0] addr_rd_ch1;
  output [8 : 0] addr_rd_ch2;
  output [15 : 0] ch1_rd_i;
  output [15 : 0] ch1_rd_r;
  input [8 : 0] addr_wr;
  input [15 : 0] ch2_to_rd_i;
  input [15 : 0] ch1_to_rd_i;
  input [15 : 0] ch2_to_rd_r;
  input [15 : 0] ch1_to_rd_r;
  wire \Mcount_count_lut[0] ;
  wire count_cmp_eq0000_inv;
  wire N01;
  wire clk_BUFGP;
  wire \Mcount_count_cy[3] ;
  wire rst_inv;
  wire \Mcount_count_cy[7] ;
  wire N22;
  wire addr_wr_0_IBUF_858;
  wire \addr_rd_ch1_add0002<0>_0 ;
  wire addr_wr_1_IBUF_860;
  wire \addr_rd_ch1_add0002<1>_0 ;
  wire addr_wr_2_IBUF_862;
  wire \addr_rd_ch1_add0002<2>_0 ;
  wire \Madd_addr_rd_ch1_add0002_cy[3] ;
  wire addr_wr_3_IBUF_865;
  wire \addr_rd_ch1_add0002<3>_0 ;
  wire addr_wr_4_IBUF_867;
  wire \addr_rd_ch1_add0002<4>_0 ;
  wire addr_wr_5_IBUF_869;
  wire \addr_rd_ch1_add0002<5>_0 ;
  wire addr_wr_6_IBUF_871;
  wire \addr_rd_ch1_add0002<6>_0 ;
  wire \Madd_addr_rd_ch1_add0002_cy[7] ;
  wire addr_wr_7_IBUF_874;
  wire \addr_rd_ch1_add0002<7>_0 ;
  wire addr_wr_8_IBUF_876;
  wire \addr_rd_ch1_add0002<8>_0 ;
  wire \addr_rd_ch1_addsub0001<0>_0 ;
  wire \addr_rd_ch1_addsub0001<1>_0 ;
  wire \addr_rd_ch1_addsub0001<2>_0 ;
  wire \Madd_addr_rd_ch1_addsub0001_cy[3] ;
  wire \addr_rd_ch1_addsub0001<3>_0 ;
  wire \addr_rd_ch1_addsub0001<4>_0 ;
  wire \Msub_addr_rd_ch1_addsub0000_cy<5>_0 ;
  wire \addr_rd_ch1_addsub0001<6>_0 ;
  wire \Madd_addr_rd_ch1_addsub0001_cy[7] ;
  wire \Msub_addr_rd_ch1_addsub0000_lut<7>_0 ;
  wire \Madd_addr_rd_ch2_addsub0001_cy<8>_0 ;
  wire \Madd_addr_rd_ch2_addsub0001_lut<9>_0 ;
  wire addr_rd_ch1_0_949;
  wire addr_rd_ch1_1_950;
  wire addr_rd_ch1_2_951;
  wire addr_rd_ch1_3_952;
  wire addr_rd_ch2_0_953;
  wire addr_rd_ch1_4_954;
  wire addr_rd_ch2_1_955;
  wire addr_rd_ch1_5_956;
  wire addr_rd_ch2_2_957;
  wire addr_rd_ch1_6_958;
  wire addr_rd_ch2_3_960;
  wire addr_rd_ch1_7_961;
  wire addr_rd_ch2_4_963;
  wire addr_rd_ch1_8_964;
  wire addr_rd_ch2_5_966;
  wire N2;
  wire addr_rd_ch2_6_969;
  wire addr_rd_ch2_7_971;
  wire addr_rd_ch2_8_973;
  wire \Mcount_count_lut<0>_rt_36 ;
  wire \Mcount_count_lut[1] ;
  wire \Mcount_count_lut[2] ;
  wire Mcount_count;
  wire Mcount_count1;
  wire Mcount_count2;
  wire Mcount_count3;
  wire \Mcount_count_lut[3] ;
  wire \Mcount_count_lut[4] ;
  wire \count<5>_rt_62 ;
  wire \count<6>_rt_58 ;
  wire Mcount_count4;
  wire Mcount_count5;
  wire Mcount_count6;
  wire Mcount_count7;
  wire \Mcount_count_lut[7] ;
  wire \count<8>_rt_81 ;
  wire Mcount_count8;
  wire \addr_rd_ch1_addsub0001[0] ;
  wire \addr_rd_ch1_addsub0001[1] ;
  wire \addr_rd_ch1_addsub0001[2] ;
  wire \addr_rd_ch1_addsub0001[3] ;
  wire \addr_rd_ch1_addsub0001[4] ;
  wire \addr_rd_ch1_addsub0001[6] ;
  wire \ch1_to_rd_r<4>/IBUF ;
  wire \ch1_to_rd_r<5>/IBUF ;
  wire \ch1_to_rd_r<6>/IBUF ;
  wire \ch1_to_rd_r<7>/IBUF ;
  wire \ch1_to_rd_r<8>/IBUF ;
  wire \addr_wr<0>/IBUF ;
  wire \ch1_to_rd_r<9>/IBUF ;
  wire \addr_wr<1>/IBUF ;
  wire \clk/IBUF ;
  wire \addr_wr<2>/IBUF ;
  wire \addr_wr<3>/IBUF ;
  wire \addr_wr<4>/IBUF ;
  wire \addr_wr<5>/IBUF ;
  wire \ch2_to_rd_r<0>/IBUF ;
  wire \addr_wr<6>/IBUF ;
  wire \ch1_to_rd_i<0>/IBUF ;
  wire \ch2_to_rd_r<1>/IBUF ;
  wire \ch1_to_rd_r<10>/IBUF ;
  wire \addr_wr<7>/IBUF ;
  wire \ch1_to_rd_i<1>/IBUF ;
  wire \ch2_to_rd_r<2>/IBUF ;
  wire \ch1_to_rd_r<11>/IBUF ;
  wire \addr_wr<8>/IBUF ;
  wire \ch1_to_rd_i<2>/IBUF ;
  wire \ch2_to_rd_r<3>/IBUF ;
  wire \ch1_to_rd_r<12>/IBUF ;
  wire \ch1_to_rd_i<3>/IBUF ;
  wire \ch2_to_rd_r<4>/IBUF ;
  wire \ch1_to_rd_r<13>/IBUF ;
  wire \ch1_to_rd_i<4>/IBUF ;
  wire \ch2_to_rd_r<5>/IBUF ;
  wire \ch1_to_rd_r<14>/IBUF ;
  wire \ch1_to_rd_i<5>/IBUF ;
  wire \ch2_to_rd_r<6>/IBUF ;
  wire \ch1_to_rd_r<15>/IBUF ;
  wire \ch1_to_rd_i<6>/IBUF ;
  wire \ch2_to_rd_r<7>/IBUF ;
  wire \ch2_to_rd_i<10>/IBUF ;
  wire \ch1_to_rd_i<7>/IBUF ;
  wire \ch2_to_rd_r<8>/IBUF ;
  wire \ch2_to_rd_i<11>/IBUF ;
  wire \ch1_to_rd_i<8>/IBUF ;
  wire \ch2_to_rd_r<9>/IBUF ;
  wire \ch2_to_rd_i<12>/IBUF ;
  wire \ch1_to_rd_i<9>/IBUF ;
  wire \ch2_to_rd_i<13>/IBUF ;
  wire \ch2_to_rd_i<14>/IBUF ;
  wire \ch2_to_rd_i<15>/IBUF ;
  wire \ch2_to_rd_i<0>/IBUF ;
  wire \ch2_to_rd_i<1>/IBUF ;
  wire \ch2_to_rd_i<2>/IBUF ;
  wire \ch2_to_rd_i<3>/IBUF ;
  wire \ch2_to_rd_i<4>/IBUF ;
  wire \ch2_to_rd_i<5>/IBUF ;
  wire \ch2_to_rd_i<6>/IBUF ;
  wire \ch2_to_rd_i<7>/IBUF ;
  wire \ch2_to_rd_i<8>/IBUF ;
  wire \ch2_to_rd_i<9>/IBUF ;
  wire \ch2_to_rd_r<10>/IBUF ;
  wire \ch2_to_rd_r<11>/IBUF ;
  wire \ch1_to_rd_i<10>/IBUF ;
  wire \ch2_to_rd_r<12>/IBUF ;
  wire \ch1_to_rd_i<11>/IBUF ;
  wire \ch2_to_rd_r<13>/IBUF ;
  wire \ch1_to_rd_i<12>/IBUF ;
  wire \ch2_to_rd_r<14>/IBUF ;
  wire \ch1_to_rd_i<13>/IBUF ;
  wire \ch2_to_rd_r<15>/IBUF ;
  wire \ch1_to_rd_i<14>/IBUF ;
  wire \ch1_to_rd_i<15>/IBUF ;
  wire \ch1_to_rd_r<0>/IBUF ;
  wire \rst/IBUF ;
  wire \ch1_to_rd_r<1>/IBUF ;
  wire \ch1_to_rd_r<2>/IBUF ;
  wire \ch1_to_rd_r<3>/IBUF ;
  wire VCC;
  wire GND;
  wire \NLW_Mcount_count_cy<3>_CO[0]_UNCONNECTED ;
  wire \NLW_Mcount_count_cy<3>_CO[1]_UNCONNECTED ;
  wire \NLW_Mcount_count_cy<3>_CO[2]_UNCONNECTED ;
  wire \NLW_N0.SLICEL_A5LUT_O_UNCONNECTED ;
  wire \NLW_Mcount_count_cy<7>_CO[0]_UNCONNECTED ;
  wire \NLW_Mcount_count_cy<7>_CO[1]_UNCONNECTED ;
  wire \NLW_Mcount_count_cy<7>_CO[2]_UNCONNECTED ;
  wire \NLW_N0_7.SLICEL_C5LUT_O_UNCONNECTED ;
  wire \NLW_N0_6.SLICEL_B5LUT_O_UNCONNECTED ;
  wire \NLW_Mcount_count_xor<8>_CO[0]_UNCONNECTED ;
  wire \NLW_Mcount_count_xor<8>_CO[1]_UNCONNECTED ;
  wire \NLW_Mcount_count_xor<8>_CO[2]_UNCONNECTED ;
  wire \NLW_Mcount_count_xor<8>_CO[3]_UNCONNECTED ;
  wire \NLW_Mcount_count_xor<8>_DI[0]_UNCONNECTED ;
  wire \NLW_Mcount_count_xor<8>_DI[1]_UNCONNECTED ;
  wire \NLW_Mcount_count_xor<8>_DI[2]_UNCONNECTED ;
  wire \NLW_Mcount_count_xor<8>_DI[3]_UNCONNECTED ;
  wire \NLW_Mcount_count_xor<8>_O[1]_UNCONNECTED ;
  wire \NLW_Mcount_count_xor<8>_O[2]_UNCONNECTED ;
  wire \NLW_Mcount_count_xor<8>_O[3]_UNCONNECTED ;
  wire \NLW_Mcount_count_xor<8>_S[1]_UNCONNECTED ;
  wire \NLW_Mcount_count_xor<8>_S[2]_UNCONNECTED ;
  wire \NLW_Mcount_count_xor<8>_S[3]_UNCONNECTED ;
  wire \NLW_ProtoComp3.CYINITGND_O_UNCONNECTED ;
  wire \NLW_Madd_addr_rd_ch1_add0002_cy<3>_CO[0]_UNCONNECTED ;
  wire \NLW_Madd_addr_rd_ch1_add0002_cy<3>_CO[1]_UNCONNECTED ;
  wire \NLW_Madd_addr_rd_ch1_add0002_cy<3>_CO[2]_UNCONNECTED ;
  wire \NLW_Madd_addr_rd_ch1_add0002_cy<7>_CO[0]_UNCONNECTED ;
  wire \NLW_Madd_addr_rd_ch1_add0002_cy<7>_CO[1]_UNCONNECTED ;
  wire \NLW_Madd_addr_rd_ch1_add0002_cy<7>_CO[2]_UNCONNECTED ;
  wire \NLW_Madd_addr_rd_ch1_add0002_xor<8>_CO[0]_UNCONNECTED ;
  wire \NLW_Madd_addr_rd_ch1_add0002_xor<8>_CO[1]_UNCONNECTED ;
  wire \NLW_Madd_addr_rd_ch1_add0002_xor<8>_CO[2]_UNCONNECTED ;
  wire \NLW_Madd_addr_rd_ch1_add0002_xor<8>_CO[3]_UNCONNECTED ;
  wire \NLW_Madd_addr_rd_ch1_add0002_xor<8>_DI[0]_UNCONNECTED ;
  wire \NLW_Madd_addr_rd_ch1_add0002_xor<8>_DI[1]_UNCONNECTED ;
  wire \NLW_Madd_addr_rd_ch1_add0002_xor<8>_DI[2]_UNCONNECTED ;
  wire \NLW_Madd_addr_rd_ch1_add0002_xor<8>_DI[3]_UNCONNECTED ;
  wire \NLW_Madd_addr_rd_ch1_add0002_xor<8>_O[1]_UNCONNECTED ;
  wire \NLW_Madd_addr_rd_ch1_add0002_xor<8>_O[2]_UNCONNECTED ;
  wire \NLW_Madd_addr_rd_ch1_add0002_xor<8>_O[3]_UNCONNECTED ;
  wire \NLW_Madd_addr_rd_ch1_add0002_xor<8>_S[1]_UNCONNECTED ;
  wire \NLW_Madd_addr_rd_ch1_add0002_xor<8>_S[2]_UNCONNECTED ;
  wire \NLW_Madd_addr_rd_ch1_add0002_xor<8>_S[3]_UNCONNECTED ;
  wire \NLW_ProtoComp3.CYINITGND.1_O_UNCONNECTED ;
  wire \NLW_Madd_addr_rd_ch1_addsub0001_cy<3>_CO[0]_UNCONNECTED ;
  wire \NLW_Madd_addr_rd_ch1_addsub0001_cy<3>_CO[1]_UNCONNECTED ;
  wire \NLW_Madd_addr_rd_ch1_addsub0001_cy<3>_CO[2]_UNCONNECTED ;
  wire \NLW_Madd_addr_rd_ch1_addsub0001_cy<7>_CO[0]_UNCONNECTED ;
  wire \NLW_Madd_addr_rd_ch1_addsub0001_cy<7>_CO[1]_UNCONNECTED ;
  wire \NLW_Madd_addr_rd_ch1_addsub0001_cy<7>_CO[2]_UNCONNECTED ;
  wire \NLW_Madd_addr_rd_ch1_addsub0001_cy<8>_CO[0]_UNCONNECTED ;
  wire \NLW_Madd_addr_rd_ch1_addsub0001_cy<8>_CO[1]_UNCONNECTED ;
  wire \NLW_Madd_addr_rd_ch1_addsub0001_cy<8>_CO[2]_UNCONNECTED ;
  wire \NLW_Madd_addr_rd_ch1_addsub0001_cy<8>_CO[3]_UNCONNECTED ;
  wire \NLW_Madd_addr_rd_ch1_addsub0001_cy<8>_DI[1]_UNCONNECTED ;
  wire \NLW_Madd_addr_rd_ch1_addsub0001_cy<8>_DI[2]_UNCONNECTED ;
  wire \NLW_Madd_addr_rd_ch1_addsub0001_cy<8>_DI[3]_UNCONNECTED ;
  wire \NLW_Madd_addr_rd_ch1_addsub0001_cy<8>_O[2]_UNCONNECTED ;
  wire \NLW_Madd_addr_rd_ch1_addsub0001_cy<8>_O[3]_UNCONNECTED ;
  wire \NLW_Madd_addr_rd_ch1_addsub0001_cy<8>_S[2]_UNCONNECTED ;
  wire \NLW_Madd_addr_rd_ch1_addsub0001_cy<8>_S[3]_UNCONNECTED ;
  wire \NLW_PhysOnlyGnd.SLICEL_B6LUT_O_UNCONNECTED ;
  wire [8 : 0] count;
  wire [8 : 0] Madd_addr_rd_ch1_add0002_lut;
  wire [8 : 0] addr_rd_ch1_add0002;
  wire [8 : 0] Madd_addr_rd_ch1_addsub0001_lut;
  wire [5 : 5] Msub_addr_rd_ch1_addsub0000_cy;
  wire [7 : 7] Msub_addr_rd_ch1_addsub0000_lut;
  wire [8 : 8] Madd_addr_rd_ch2_addsub0001_cy;
  wire [9 : 9] Madd_addr_rd_ch2_addsub0001_lut;
  wire [8 : 0] addr_rd_ch1_mux0000;
  wire [8 : 0] addr_rd_ch2_mux0000;
  initial $sdf_annotate("netgen/map/mem_rd_dual_map.sdf");
  X_FF #(
    .LOC ( "SLICE_X18Y34" ),
    .INIT ( 1'b0 ))
  count_3 (
    .CE(VCC),
    .CLK(clk_BUFGP),
    .I(Mcount_count3),
    .O(count[3]),
    .SET(GND),
    .RST(rst_inv)
  );
  X_LUT6 #(
    .LOC ( "SLICE_X18Y34" ),
    .INIT ( 64'hFF00FF007F00FF00 ))
  \Mcount_count_lut<3>  (
    .ADR0(count[4]),
    .ADR1(count[2]),
    .ADR2(count[1]),
    .ADR3(count[3]),
    .ADR4(count[0]),
    .ADR5(N01),
    .O(\Mcount_count_lut[3] )
  );
  X_FF #(
    .LOC ( "SLICE_X18Y34" ),
    .INIT ( 1'b0 ))
  count_2 (
    .CE(VCC),
    .CLK(clk_BUFGP),
    .I(Mcount_count2),
    .O(count[2]),
    .SET(GND),
    .RST(rst_inv)
  );
  X_CARRY4 #(
    .LOC ( "SLICE_X18Y34" ))
  \Mcount_count_cy<3>  (
    .CI(1'b0),
    .CYINIT(count_cmp_eq0000_inv),
    .CO({\Mcount_count_cy[3] , \NLW_Mcount_count_cy<3>_CO[2]_UNCONNECTED , \NLW_Mcount_count_cy<3>_CO[1]_UNCONNECTED , 
\NLW_Mcount_count_cy<3>_CO[0]_UNCONNECTED }),
    .DI({1'b0, 1'b0, 1'b0, 1'b0}),
    .O({Mcount_count3, Mcount_count2, Mcount_count1, Mcount_count}),
    .S({\Mcount_count_lut[3] , \Mcount_count_lut[2] , \Mcount_count_lut[1] , \Mcount_count_lut<0>_rt_36 })
  );
  X_LUT6 #(
    .LOC ( "SLICE_X18Y34" ),
    .INIT ( 64'hFF00FF007F00FF00 ))
  \Mcount_count_lut<2>  (
    .ADR0(count[4]),
    .ADR1(count[3]),
    .ADR2(count[1]),
    .ADR3(count[2]),
    .ADR4(count[0]),
    .ADR5(N01),
    .O(\Mcount_count_lut[2] )
  );
  X_FF #(
    .LOC ( "SLICE_X18Y34" ),
    .INIT ( 1'b0 ))
  count_1 (
    .CE(VCC),
    .CLK(clk_BUFGP),
    .I(Mcount_count1),
    .O(count[1]),
    .SET(GND),
    .RST(rst_inv)
  );
  X_LUT6 #(
    .LOC ( "SLICE_X18Y34" ),
    .INIT ( 64'hFF00FF007F00FF00 ))
  \Mcount_count_lut<1>  (
    .ADR0(count[4]),
    .ADR1(count[3]),
    .ADR2(count[2]),
    .ADR3(count[1]),
    .ADR4(count[0]),
    .ADR5(N01),
    .O(\Mcount_count_lut[1] )
  );
  X_FF #(
    .LOC ( "SLICE_X18Y34" ),
    .INIT ( 1'b0 ))
  count_0 (
    .CE(VCC),
    .CLK(clk_BUFGP),
    .I(Mcount_count),
    .O(count[0]),
    .SET(GND),
    .RST(rst_inv)
  );
  X_LUT6 #(
    .LOC ( "SLICE_X18Y34" ),
    .INIT ( 64'hFFFF0000FFFF0000 ))
  \Mcount_count_lut<0>_rt  (
    .ADR0(1'b1),
    .ADR1(1'b1),
    .ADR2(1'b1),
    .ADR3(1'b1),
    .ADR4(\Mcount_count_lut[0] ),
    .ADR5(1'b1),
    .O(\Mcount_count_lut<0>_rt_36 )
  );
  X_LUT5 #(
    .LOC ( "SLICE_X18Y34" ),
    .INIT ( 32'h00000000 ))
  \N0.SLICEL_A5LUT  (
    .ADR0(1'b1),
    .ADR1(1'b1),
    .ADR2(1'b1),
    .ADR3(1'b1),
    .ADR4(1'b1),
    .O(\NLW_N0.SLICEL_A5LUT_O_UNCONNECTED )
  );
  X_FF #(
    .LOC ( "SLICE_X18Y35" ),
    .INIT ( 1'b0 ))
  count_7 (
    .CE(VCC),
    .CLK(clk_BUFGP),
    .I(Mcount_count7),
    .O(count[7]),
    .SET(GND),
    .RST(rst_inv)
  );
  X_LUT6 #(
    .LOC ( "SLICE_X18Y35" ),
    .INIT ( 64'hFF00FF007F00FF00 ))
  \Mcount_count_lut<7>  (
    .ADR0(count[2]),
    .ADR1(count[1]),
    .ADR2(count[0]),
    .ADR3(count[7]),
    .ADR4(N22),
    .ADR5(N01),
    .O(\Mcount_count_lut[7] )
  );
  X_FF #(
    .LOC ( "SLICE_X18Y35" ),
    .INIT ( 1'b0 ))
  count_6 (
    .CE(VCC),
    .CLK(clk_BUFGP),
    .I(Mcount_count6),
    .O(count[6]),
    .SET(GND),
    .RST(rst_inv)
  );
  X_CARRY4 #(
    .LOC ( "SLICE_X18Y35" ))
  \Mcount_count_cy<7>  (
    .CI(\Mcount_count_cy[3] ),
    .CYINIT(1'b0),
    .CO({\Mcount_count_cy[7] , \NLW_Mcount_count_cy<7>_CO[2]_UNCONNECTED , \NLW_Mcount_count_cy<7>_CO[1]_UNCONNECTED , 
\NLW_Mcount_count_cy<7>_CO[0]_UNCONNECTED }),
    .DI({1'b0, 1'b0, 1'b0, 1'b0}),
    .O({Mcount_count7, Mcount_count6, Mcount_count5, Mcount_count4}),
    .S({\Mcount_count_lut[7] , \count<6>_rt_58 , \count<5>_rt_62 , \Mcount_count_lut[4] })
  );
  X_LUT6 #(
    .LOC ( "SLICE_X18Y35" ),
    .INIT ( 64'hFF00FF00FF00FF00 ))
  \count<6>_rt  (
    .ADR0(1'b1),
    .ADR1(1'b1),
    .ADR2(1'b1),
    .ADR3(count[6]),
    .ADR4(1'b1),
    .ADR5(1'b1),
    .O(\count<6>_rt_58 )
  );
  X_LUT5 #(
    .LOC ( "SLICE_X18Y35" ),
    .INIT ( 32'h00000000 ))
  \N0_7.SLICEL_C5LUT  (
    .ADR0(1'b1),
    .ADR1(1'b1),
    .ADR2(1'b1),
    .ADR3(1'b1),
    .ADR4(1'b1),
    .O(\NLW_N0_7.SLICEL_C5LUT_O_UNCONNECTED )
  );
  X_FF #(
    .LOC ( "SLICE_X18Y35" ),
    .INIT ( 1'b0 ))
  count_5 (
    .CE(VCC),
    .CLK(clk_BUFGP),
    .I(Mcount_count5),
    .O(count[5]),
    .SET(GND),
    .RST(rst_inv)
  );
  X_LUT6 #(
    .LOC ( "SLICE_X18Y35" ),
    .INIT ( 64'hFF00FF00FF00FF00 ))
  \count<5>_rt  (
    .ADR0(1'b1),
    .ADR1(1'b1),
    .ADR2(1'b1),
    .ADR3(count[5]),
    .ADR4(1'b1),
    .ADR5(1'b1),
    .O(\count<5>_rt_62 )
  );
  X_LUT5 #(
    .LOC ( "SLICE_X18Y35" ),
    .INIT ( 32'h00000000 ))
  \N0_6.SLICEL_B5LUT  (
    .ADR0(1'b1),
    .ADR1(1'b1),
    .ADR2(1'b1),
    .ADR3(1'b1),
    .ADR4(1'b1),
    .O(\NLW_N0_6.SLICEL_B5LUT_O_UNCONNECTED )
  );
  X_FF #(
    .LOC ( "SLICE_X18Y35" ),
    .INIT ( 1'b0 ))
  count_4 (
    .CE(VCC),
    .CLK(clk_BUFGP),
    .I(Mcount_count4),
    .O(count[4]),
    .SET(GND),
    .RST(rst_inv)
  );
  X_LUT6 #(
    .LOC ( "SLICE_X18Y35" ),
    .INIT ( 64'hFF00FF007F00FF00 ))
  \Mcount_count_lut<4>  (
    .ADR0(count[3]),
    .ADR1(count[2]),
    .ADR2(count[1]),
    .ADR3(count[4]),
    .ADR4(count[0]),
    .ADR5(N01),
    .O(\Mcount_count_lut[4] )
  );
  X_CARRY4 #(
    .LOC ( "SLICE_X18Y36" ))
  \Mcount_count_xor<8>  (
    .CI(\Mcount_count_cy[7] ),
    .CYINIT(1'b0),
    .CO({\NLW_Mcount_count_xor<8>_CO[3]_UNCONNECTED , \NLW_Mcount_count_xor<8>_CO[2]_UNCONNECTED , \NLW_Mcount_count_xor<8>_CO[1]_UNCONNECTED , 
\NLW_Mcount_count_xor<8>_CO[0]_UNCONNECTED }),
    .DI({\NLW_Mcount_count_xor<8>_DI[3]_UNCONNECTED , \NLW_Mcount_count_xor<8>_DI[2]_UNCONNECTED , \NLW_Mcount_count_xor<8>_DI[1]_UNCONNECTED , 
\NLW_Mcount_count_xor<8>_DI[0]_UNCONNECTED }),
    .O({\NLW_Mcount_count_xor<8>_O[3]_UNCONNECTED , \NLW_Mcount_count_xor<8>_O[2]_UNCONNECTED , \NLW_Mcount_count_xor<8>_O[1]_UNCONNECTED , 
Mcount_count8}),
    .S({\NLW_Mcount_count_xor<8>_S[3]_UNCONNECTED , \NLW_Mcount_count_xor<8>_S[2]_UNCONNECTED , \NLW_Mcount_count_xor<8>_S[1]_UNCONNECTED , 
\count<8>_rt_81 })
  );
  X_FF #(
    .LOC ( "SLICE_X18Y36" ),
    .INIT ( 1'b0 ))
  count_8 (
    .CE(VCC),
    .CLK(clk_BUFGP),
    .I(Mcount_count8),
    .O(count[8]),
    .SET(GND),
    .RST(rst_inv)
  );
  X_LUT6 #(
    .LOC ( "SLICE_X18Y36" ),
    .INIT ( 64'hFF00FF00FF00FF00 ))
  \count<8>_rt  (
    .ADR0(1'b1),
    .ADR1(1'b1),
    .ADR2(1'b1),
    .ADR3(count[8]),
    .ADR4(1'b1),
    .ADR5(1'b1),
    .O(\count<8>_rt_81 )
  );
  X_BUF   \Madd_addr_rd_ch1_add0002_cy<3>/Madd_addr_rd_ch1_add0002_cy<3>_DMUX_Delay  (
    .I(addr_rd_ch1_add0002[3]),
    .O(\addr_rd_ch1_add0002<3>_0 )
  );
  X_BUF   \Madd_addr_rd_ch1_add0002_cy<3>/Madd_addr_rd_ch1_add0002_cy<3>_CMUX_Delay  (
    .I(addr_rd_ch1_add0002[2]),
    .O(\addr_rd_ch1_add0002<2>_0 )
  );
  X_BUF   \Madd_addr_rd_ch1_add0002_cy<3>/Madd_addr_rd_ch1_add0002_cy<3>_BMUX_Delay  (
    .I(addr_rd_ch1_add0002[1]),
    .O(\addr_rd_ch1_add0002<1>_0 )
  );
  X_BUF   \Madd_addr_rd_ch1_add0002_cy<3>/Madd_addr_rd_ch1_add0002_cy<3>_AMUX_Delay  (
    .I(addr_rd_ch1_add0002[0]),
    .O(\addr_rd_ch1_add0002<0>_0 )
  );
  X_LUT6 #(
    .LOC ( "SLICE_X6Y35" ),
    .INIT ( 64'h0000FFFFFFFF0000 ))
  \Madd_addr_rd_ch1_add0002_lut<3>  (
    .ADR0(1'b1),
    .ADR1(1'b1),
    .ADR2(1'b1),
    .ADR3(1'b1),
    .ADR4(addr_wr_3_IBUF_865),
    .ADR5(count[3]),
    .O(Madd_addr_rd_ch1_add0002_lut[3])
  );
  X_ZERO #(
    .LOC ( "SLICE_X6Y35" ))
  \ProtoComp3.CYINITGND  (
    .O(\NLW_ProtoComp3.CYINITGND_O_UNCONNECTED )
  );
  X_CARRY4 #(
    .LOC ( "SLICE_X6Y35" ))
  \Madd_addr_rd_ch1_add0002_cy<3>  (
    .CI(1'b0),
    .CYINIT(1'b0),
    .CO({\Madd_addr_rd_ch1_add0002_cy[3] , \NLW_Madd_addr_rd_ch1_add0002_cy<3>_CO[2]_UNCONNECTED , 
\NLW_Madd_addr_rd_ch1_add0002_cy<3>_CO[1]_UNCONNECTED , \NLW_Madd_addr_rd_ch1_add0002_cy<3>_CO[0]_UNCONNECTED }),
    .DI({addr_wr_3_IBUF_865, addr_wr_2_IBUF_862, addr_wr_1_IBUF_860, addr_wr_0_IBUF_858}),
    .O({addr_rd_ch1_add0002[3], addr_rd_ch1_add0002[2], addr_rd_ch1_add0002[1], addr_rd_ch1_add0002[0]}),
    .S({Madd_addr_rd_ch1_add0002_lut[3], Madd_addr_rd_ch1_add0002_lut[2], Madd_addr_rd_ch1_add0002_lut[1], Madd_addr_rd_ch1_add0002_lut[0]})
  );
  X_LUT6 #(
    .LOC ( "SLICE_X6Y35" ),
    .INIT ( 64'h0000FFFFFFFF0000 ))
  \Madd_addr_rd_ch1_add0002_lut<2>  (
    .ADR0(1'b1),
    .ADR1(1'b1),
    .ADR2(1'b1),
    .ADR3(1'b1),
    .ADR4(addr_wr_2_IBUF_862),
    .ADR5(count[2]),
    .O(Madd_addr_rd_ch1_add0002_lut[2])
  );
  X_LUT6 #(
    .LOC ( "SLICE_X6Y35" ),
    .INIT ( 64'h0000FFFFFFFF0000 ))
  \Madd_addr_rd_ch1_add0002_lut<1>  (
    .ADR0(1'b1),
    .ADR1(1'b1),
    .ADR2(1'b1),
    .ADR3(1'b1),
    .ADR4(addr_wr_1_IBUF_860),
    .ADR5(count[1]),
    .O(Madd_addr_rd_ch1_add0002_lut[1])
  );
  X_LUT6 #(
    .LOC ( "SLICE_X6Y35" ),
    .INIT ( 64'h0000FFFFFFFF0000 ))
  \Madd_addr_rd_ch1_add0002_lut<0>  (
    .ADR0(1'b1),
    .ADR1(1'b1),
    .ADR2(1'b1),
    .ADR3(1'b1),
    .ADR4(addr_wr_0_IBUF_858),
    .ADR5(count[0]),
    .O(Madd_addr_rd_ch1_add0002_lut[0])
  );
  X_BUF   \Madd_addr_rd_ch1_add0002_cy<7>/Madd_addr_rd_ch1_add0002_cy<7>_DMUX_Delay  (
    .I(addr_rd_ch1_add0002[7]),
    .O(\addr_rd_ch1_add0002<7>_0 )
  );
  X_BUF   \Madd_addr_rd_ch1_add0002_cy<7>/Madd_addr_rd_ch1_add0002_cy<7>_CMUX_Delay  (
    .I(addr_rd_ch1_add0002[6]),
    .O(\addr_rd_ch1_add0002<6>_0 )
  );
  X_BUF   \Madd_addr_rd_ch1_add0002_cy<7>/Madd_addr_rd_ch1_add0002_cy<7>_BMUX_Delay  (
    .I(addr_rd_ch1_add0002[5]),
    .O(\addr_rd_ch1_add0002<5>_0 )
  );
  X_BUF   \Madd_addr_rd_ch1_add0002_cy<7>/Madd_addr_rd_ch1_add0002_cy<7>_AMUX_Delay  (
    .I(addr_rd_ch1_add0002[4]),
    .O(\addr_rd_ch1_add0002<4>_0 )
  );
  X_LUT6 #(
    .LOC ( "SLICE_X6Y36" ),
    .INIT ( 64'h0000FFFFFFFF0000 ))
  \Madd_addr_rd_ch1_add0002_lut<7>  (
    .ADR0(1'b1),
    .ADR1(1'b1),
    .ADR2(1'b1),
    .ADR3(1'b1),
    .ADR4(addr_wr_7_IBUF_874),
    .ADR5(count[7]),
    .O(Madd_addr_rd_ch1_add0002_lut[7])
  );
  X_CARRY4 #(
    .LOC ( "SLICE_X6Y36" ))
  \Madd_addr_rd_ch1_add0002_cy<7>  (
    .CI(\Madd_addr_rd_ch1_add0002_cy[3] ),
    .CYINIT(1'b0),
    .CO({\Madd_addr_rd_ch1_add0002_cy[7] , \NLW_Madd_addr_rd_ch1_add0002_cy<7>_CO[2]_UNCONNECTED , 
\NLW_Madd_addr_rd_ch1_add0002_cy<7>_CO[1]_UNCONNECTED , \NLW_Madd_addr_rd_ch1_add0002_cy<7>_CO[0]_UNCONNECTED }),
    .DI({addr_wr_7_IBUF_874, addr_wr_6_IBUF_871, addr_wr_5_IBUF_869, addr_wr_4_IBUF_867}),
    .O({addr_rd_ch1_add0002[7], addr_rd_ch1_add0002[6], addr_rd_ch1_add0002[5], addr_rd_ch1_add0002[4]}),
    .S({Madd_addr_rd_ch1_add0002_lut[7], Madd_addr_rd_ch1_add0002_lut[6], Madd_addr_rd_ch1_add0002_lut[5], Madd_addr_rd_ch1_add0002_lut[4]})
  );
  X_LUT6 #(
    .LOC ( "SLICE_X6Y36" ),
    .INIT ( 64'h0000FFFFFFFF0000 ))
  \Madd_addr_rd_ch1_add0002_lut<6>  (
    .ADR0(1'b1),
    .ADR1(1'b1),
    .ADR2(1'b1),
    .ADR3(1'b1),
    .ADR4(addr_wr_6_IBUF_871),
    .ADR5(count[6]),
    .O(Madd_addr_rd_ch1_add0002_lut[6])
  );
  X_LUT6 #(
    .LOC ( "SLICE_X6Y36" ),
    .INIT ( 64'h0000FFFFFFFF0000 ))
  \Madd_addr_rd_ch1_add0002_lut<5>  (
    .ADR0(1'b1),
    .ADR1(1'b1),
    .ADR2(1'b1),
    .ADR3(1'b1),
    .ADR4(addr_wr_5_IBUF_869),
    .ADR5(count[5]),
    .O(Madd_addr_rd_ch1_add0002_lut[5])
  );
  X_LUT6 #(
    .LOC ( "SLICE_X6Y36" ),
    .INIT ( 64'h0000FFFFFFFF0000 ))
  \Madd_addr_rd_ch1_add0002_lut<4>  (
    .ADR0(1'b1),
    .ADR1(1'b1),
    .ADR2(1'b1),
    .ADR3(1'b1),
    .ADR4(addr_wr_4_IBUF_867),
    .ADR5(count[4]),
    .O(Madd_addr_rd_ch1_add0002_lut[4])
  );
  X_BUF   \addr_rd_ch1_add0002<8>/addr_rd_ch1_add0002<8>_AMUX_Delay  (
    .I(addr_rd_ch1_add0002[8]),
    .O(\addr_rd_ch1_add0002<8>_0 )
  );
  X_CARRY4 #(
    .LOC ( "SLICE_X6Y37" ))
  \Madd_addr_rd_ch1_add0002_xor<8>  (
    .CI(\Madd_addr_rd_ch1_add0002_cy[7] ),
    .CYINIT(1'b0),
    .CO({\NLW_Madd_addr_rd_ch1_add0002_xor<8>_CO[3]_UNCONNECTED , \NLW_Madd_addr_rd_ch1_add0002_xor<8>_CO[2]_UNCONNECTED , 
\NLW_Madd_addr_rd_ch1_add0002_xor<8>_CO[1]_UNCONNECTED , \NLW_Madd_addr_rd_ch1_add0002_xor<8>_CO[0]_UNCONNECTED }),
    .DI({\NLW_Madd_addr_rd_ch1_add0002_xor<8>_DI[3]_UNCONNECTED , \NLW_Madd_addr_rd_ch1_add0002_xor<8>_DI[2]_UNCONNECTED , 
\NLW_Madd_addr_rd_ch1_add0002_xor<8>_DI[1]_UNCONNECTED , \NLW_Madd_addr_rd_ch1_add0002_xor<8>_DI[0]_UNCONNECTED }),
    .O({\NLW_Madd_addr_rd_ch1_add0002_xor<8>_O[3]_UNCONNECTED , \NLW_Madd_addr_rd_ch1_add0002_xor<8>_O[2]_UNCONNECTED , 
\NLW_Madd_addr_rd_ch1_add0002_xor<8>_O[1]_UNCONNECTED , addr_rd_ch1_add0002[8]}),
    .S({\NLW_Madd_addr_rd_ch1_add0002_xor<8>_S[3]_UNCONNECTED , \NLW_Madd_addr_rd_ch1_add0002_xor<8>_S[2]_UNCONNECTED , 
\NLW_Madd_addr_rd_ch1_add0002_xor<8>_S[1]_UNCONNECTED , Madd_addr_rd_ch1_add0002_lut[8]})
  );
  X_LUT6 #(
    .LOC ( "SLICE_X6Y37" ),
    .INIT ( 64'h0000FFFFFFFF0000 ))
  \Madd_addr_rd_ch1_addsub0001_lut<8>  (
    .ADR0(1'b1),
    .ADR1(1'b1),
    .ADR2(1'b1),
    .ADR3(1'b1),
    .ADR4(addr_wr_8_IBUF_876),
    .ADR5(count[8]),
    .O(Madd_addr_rd_ch1_add0002_lut[8])
  );
  X_BUF   \Madd_addr_rd_ch1_addsub0001_cy<3>/Madd_addr_rd_ch1_addsub0001_cy<3>_DMUX_Delay  (
    .I(\addr_rd_ch1_addsub0001[3] ),
    .O(\addr_rd_ch1_addsub0001<3>_0 )
  );
  X_BUF   \Madd_addr_rd_ch1_addsub0001_cy<3>/Madd_addr_rd_ch1_addsub0001_cy<3>_CMUX_Delay  (
    .I(\addr_rd_ch1_addsub0001[2] ),
    .O(\addr_rd_ch1_addsub0001<2>_0 )
  );
  X_BUF   \Madd_addr_rd_ch1_addsub0001_cy<3>/Madd_addr_rd_ch1_addsub0001_cy<3>_BMUX_Delay  (
    .I(\addr_rd_ch1_addsub0001[1] ),
    .O(\addr_rd_ch1_addsub0001<1>_0 )
  );
  X_BUF   \Madd_addr_rd_ch1_addsub0001_cy<3>/Madd_addr_rd_ch1_addsub0001_cy<3>_AMUX_Delay  (
    .I(\addr_rd_ch1_addsub0001[0] ),
    .O(\addr_rd_ch1_addsub0001<0>_0 )
  );
  X_LUT6 #(
    .LOC ( "SLICE_X7Y34" ),
    .INIT ( 64'h0000FFFFFFFF0000 ))
  \Madd_addr_rd_ch1_addsub0001_lut<3>  (
    .ADR0(1'b1),
    .ADR1(1'b1),
    .ADR2(1'b1),
    .ADR3(1'b1),
    .ADR4(addr_wr_3_IBUF_865),
    .ADR5(count[3]),
    .O(Madd_addr_rd_ch1_addsub0001_lut[3])
  );
  X_ZERO #(
    .LOC ( "SLICE_X7Y34" ))
  \ProtoComp3.CYINITGND.1  (
    .O(\NLW_ProtoComp3.CYINITGND.1_O_UNCONNECTED )
  );
  X_CARRY4 #(
    .LOC ( "SLICE_X7Y34" ))
  \Madd_addr_rd_ch1_addsub0001_cy<3>  (
    .CI(1'b0),
    .CYINIT(1'b0),
    .CO({\Madd_addr_rd_ch1_addsub0001_cy[3] , \NLW_Madd_addr_rd_ch1_addsub0001_cy<3>_CO[2]_UNCONNECTED , 
\NLW_Madd_addr_rd_ch1_addsub0001_cy<3>_CO[1]_UNCONNECTED , \NLW_Madd_addr_rd_ch1_addsub0001_cy<3>_CO[0]_UNCONNECTED }),
    .DI({addr_wr_3_IBUF_865, addr_wr_2_IBUF_862, addr_wr_1_IBUF_860, addr_wr_0_IBUF_858}),
    .O({\addr_rd_ch1_addsub0001[3] , \addr_rd_ch1_addsub0001[2] , \addr_rd_ch1_addsub0001[1] , \addr_rd_ch1_addsub0001[0] }),
    .S({Madd_addr_rd_ch1_addsub0001_lut[3], Madd_addr_rd_ch1_addsub0001_lut[2], Madd_addr_rd_ch1_addsub0001_lut[1], Madd_addr_rd_ch1_addsub0001_lut[0]
})
  );
  X_LUT6 #(
    .LOC ( "SLICE_X7Y34" ),
    .INIT ( 64'h0000FFFFFFFF0000 ))
  \Madd_addr_rd_ch1_addsub0001_lut<2>  (
    .ADR0(1'b1),
    .ADR1(1'b1),
    .ADR2(1'b1),
    .ADR3(1'b1),
    .ADR4(addr_wr_2_IBUF_862),
    .ADR5(count[2]),
    .O(Madd_addr_rd_ch1_addsub0001_lut[2])
  );
  X_LUT6 #(
    .LOC ( "SLICE_X7Y34" ),
    .INIT ( 64'h0000FFFFFFFF0000 ))
  \Madd_addr_rd_ch1_addsub0001_lut<1>  (
    .ADR0(1'b1),
    .ADR1(1'b1),
    .ADR2(1'b1),
    .ADR3(1'b1),
    .ADR4(addr_wr_1_IBUF_860),
    .ADR5(count[1]),
    .O(Madd_addr_rd_ch1_addsub0001_lut[1])
  );
  X_LUT6 #(
    .LOC ( "SLICE_X7Y34" ),
    .INIT ( 64'h0000FFFFFFFF0000 ))
  \Madd_addr_rd_ch1_addsub0001_lut<0>  (
    .ADR0(1'b1),
    .ADR1(1'b1),
    .ADR2(1'b1),
    .ADR3(1'b1),
    .ADR4(addr_wr_0_IBUF_858),
    .ADR5(count[0]),
    .O(Madd_addr_rd_ch1_addsub0001_lut[0])
  );
  X_BUF   \Madd_addr_rd_ch1_addsub0001_cy<7>/Madd_addr_rd_ch1_addsub0001_cy<7>_DMUX_Delay  (
    .I(Msub_addr_rd_ch1_addsub0000_lut[7]),
    .O(\Msub_addr_rd_ch1_addsub0000_lut<7>_0 )
  );
  X_BUF   \Madd_addr_rd_ch1_addsub0001_cy<7>/Madd_addr_rd_ch1_addsub0001_cy<7>_CMUX_Delay  (
    .I(\addr_rd_ch1_addsub0001[6] ),
    .O(\addr_rd_ch1_addsub0001<6>_0 )
  );
  X_BUF   \Madd_addr_rd_ch1_addsub0001_cy<7>/Madd_addr_rd_ch1_addsub0001_cy<7>_BMUX_Delay  (
    .I(Msub_addr_rd_ch1_addsub0000_cy[5]),
    .O(\Msub_addr_rd_ch1_addsub0000_cy<5>_0 )
  );
  X_BUF   \Madd_addr_rd_ch1_addsub0001_cy<7>/Madd_addr_rd_ch1_addsub0001_cy<7>_AMUX_Delay  (
    .I(\addr_rd_ch1_addsub0001[4] ),
    .O(\addr_rd_ch1_addsub0001<4>_0 )
  );
  X_LUT6 #(
    .LOC ( "SLICE_X7Y35" ),
    .INIT ( 64'h0000FFFFFFFF0000 ))
  \Madd_addr_rd_ch1_addsub0001_lut<7>  (
    .ADR0(1'b1),
    .ADR1(1'b1),
    .ADR2(1'b1),
    .ADR3(1'b1),
    .ADR4(addr_wr_7_IBUF_874),
    .ADR5(count[7]),
    .O(Madd_addr_rd_ch1_addsub0001_lut[7])
  );
  X_CARRY4 #(
    .LOC ( "SLICE_X7Y35" ))
  \Madd_addr_rd_ch1_addsub0001_cy<7>  (
    .CI(\Madd_addr_rd_ch1_addsub0001_cy[3] ),
    .CYINIT(1'b0),
    .CO({\Madd_addr_rd_ch1_addsub0001_cy[7] , \NLW_Madd_addr_rd_ch1_addsub0001_cy<7>_CO[2]_UNCONNECTED , 
\NLW_Madd_addr_rd_ch1_addsub0001_cy<7>_CO[1]_UNCONNECTED , \NLW_Madd_addr_rd_ch1_addsub0001_cy<7>_CO[0]_UNCONNECTED }),
    .DI({addr_wr_7_IBUF_874, addr_wr_6_IBUF_871, addr_wr_5_IBUF_869, addr_wr_4_IBUF_867}),
    .O({Msub_addr_rd_ch1_addsub0000_lut[7], \addr_rd_ch1_addsub0001[6] , Msub_addr_rd_ch1_addsub0000_cy[5], \addr_rd_ch1_addsub0001[4] }),
    .S({Madd_addr_rd_ch1_addsub0001_lut[7], Madd_addr_rd_ch1_addsub0001_lut[6], Madd_addr_rd_ch1_addsub0001_lut[5], Madd_addr_rd_ch1_addsub0001_lut[4]
})
  );
  X_LUT6 #(
    .LOC ( "SLICE_X7Y35" ),
    .INIT ( 64'h0000FFFFFFFF0000 ))
  \Madd_addr_rd_ch1_addsub0001_lut<6>  (
    .ADR0(1'b1),
    .ADR1(1'b1),
    .ADR2(1'b1),
    .ADR3(1'b1),
    .ADR4(addr_wr_6_IBUF_871),
    .ADR5(count[6]),
    .O(Madd_addr_rd_ch1_addsub0001_lut[6])
  );
  X_LUT6 #(
    .LOC ( "SLICE_X7Y35" ),
    .INIT ( 64'h0000FFFFFFFF0000 ))
  \Madd_addr_rd_ch1_addsub0001_lut<5>  (
    .ADR0(1'b1),
    .ADR1(1'b1),
    .ADR2(1'b1),
    .ADR3(1'b1),
    .ADR4(addr_wr_5_IBUF_869),
    .ADR5(count[5]),
    .O(Madd_addr_rd_ch1_addsub0001_lut[5])
  );
  X_LUT6 #(
    .LOC ( "SLICE_X7Y35" ),
    .INIT ( 64'h0000FFFFFFFF0000 ))
  \Madd_addr_rd_ch1_addsub0001_lut<4>  (
    .ADR0(1'b1),
    .ADR1(1'b1),
    .ADR2(1'b1),
    .ADR3(1'b1),
    .ADR4(addr_wr_4_IBUF_867),
    .ADR5(count[4]),
    .O(Madd_addr_rd_ch1_addsub0001_lut[4])
  );
  X_BUF   \Madd_addr_rd_ch2_addsub0001_lut<9>/Madd_addr_rd_ch2_addsub0001_lut<9>_BMUX_Delay  (
    .I(Madd_addr_rd_ch2_addsub0001_lut[9]),
    .O(\Madd_addr_rd_ch2_addsub0001_lut<9>_0 )
  );
  X_BUF   \Madd_addr_rd_ch2_addsub0001_lut<9>/Madd_addr_rd_ch2_addsub0001_lut<9>_AMUX_Delay  (
    .I(Madd_addr_rd_ch2_addsub0001_cy[8]),
    .O(\Madd_addr_rd_ch2_addsub0001_cy<8>_0 )
  );
  X_CARRY4 #(
    .LOC ( "SLICE_X7Y36" ))
  \Madd_addr_rd_ch1_addsub0001_cy<8>  (
    .CI(\Madd_addr_rd_ch1_addsub0001_cy[7] ),
    .CYINIT(1'b0),
    .CO({\NLW_Madd_addr_rd_ch1_addsub0001_cy<8>_CO[3]_UNCONNECTED , \NLW_Madd_addr_rd_ch1_addsub0001_cy<8>_CO[2]_UNCONNECTED , 
\NLW_Madd_addr_rd_ch1_addsub0001_cy<8>_CO[1]_UNCONNECTED , \NLW_Madd_addr_rd_ch1_addsub0001_cy<8>_CO[0]_UNCONNECTED }),
    .DI({\NLW_Madd_addr_rd_ch1_addsub0001_cy<8>_DI[3]_UNCONNECTED , \NLW_Madd_addr_rd_ch1_addsub0001_cy<8>_DI[2]_UNCONNECTED , 
\NLW_Madd_addr_rd_ch1_addsub0001_cy<8>_DI[1]_UNCONNECTED , addr_wr_8_IBUF_876}),
    .O({\NLW_Madd_addr_rd_ch1_addsub0001_cy<8>_O[3]_UNCONNECTED , \NLW_Madd_addr_rd_ch1_addsub0001_cy<8>_O[2]_UNCONNECTED , 
Madd_addr_rd_ch2_addsub0001_lut[9], Madd_addr_rd_ch2_addsub0001_cy[8]}),
    .S({\NLW_Madd_addr_rd_ch1_addsub0001_cy<8>_S[3]_UNCONNECTED , \NLW_Madd_addr_rd_ch1_addsub0001_cy<8>_S[2]_UNCONNECTED , 1'b0, 
Madd_addr_rd_ch1_addsub0001_lut[8]})
  );
  X_LUT6 #(
    .LOC ( "SLICE_X7Y36" ),
    .INIT ( 64'h0000000000000000 ))
  \PhysOnlyGnd.SLICEL_B6LUT  (
    .ADR0(1'b1),
    .ADR1(1'b1),
    .ADR2(1'b1),
    .ADR3(1'b1),
    .ADR4(1'b1),
    .ADR5(1'b1),
    .O(\NLW_PhysOnlyGnd.SLICEL_B6LUT_O_UNCONNECTED )
  );
  X_LUT6 #(
    .LOC ( "SLICE_X7Y36" ),
    .INIT ( 64'h0000FFFFFFFF0000 ))
  \Madd_addr_rd_ch1_addsub0001_lut<8>1  (
    .ADR0(1'b1),
    .ADR1(1'b1),
    .ADR2(1'b1),
    .ADR3(1'b1),
    .ADR4(addr_wr_8_IBUF_876),
    .ADR5(count[8]),
    .O(Madd_addr_rd_ch1_addsub0001_lut[8])
  );
  X_OPAD #(
    .LOC ( "IOB_X0Y11" ))
  \ch2_rd_r<0>/PAD  (
    .PAD(ch2_rd_r[0])
  );
  X_OBUF #(
    .LOC ( "IOB_X0Y11" ))
  ch2_rd_r_0_OBUF (
    .I(\ch2_to_rd_r<0>/IBUF ),
    .O(ch2_rd_r[0])
  );
  X_IPAD #(
    .LOC ( "IOB_X0Y60" ))
  \ch1_to_rd_r<4>/PAD  (
    .PAD(ch1_to_rd_r[4])
  );
  X_BUF #(
    .LOC ( "IOB_X0Y60" ))
  ch1_to_rd_r_4_IBUF (
    .I(ch1_to_rd_r[4]),
    .O(\ch1_to_rd_r<4>/IBUF )
  );
  X_OPAD #(
    .LOC ( "IOB_X1Y110" ))
  \ch2_rd_i<13>/PAD  (
    .PAD(ch2_rd_i[13])
  );
  X_OBUF #(
    .LOC ( "IOB_X1Y110" ))
  ch2_rd_i_13_OBUF (
    .I(\ch2_to_rd_i<13>/IBUF ),
    .O(ch2_rd_i[13])
  );
  X_OPAD #(
    .LOC ( "IOB_X0Y0" ))
  \ch2_rd_r<1>/PAD  (
    .PAD(ch2_rd_r[1])
  );
  X_OBUF #(
    .LOC ( "IOB_X0Y0" ))
  ch2_rd_r_1_OBUF (
    .I(\ch2_to_rd_r<1>/IBUF ),
    .O(ch2_rd_r[1])
  );
  X_IPAD #(
    .LOC ( "IOB_X1Y37" ))
  \ch1_to_rd_r<5>/PAD  (
    .PAD(ch1_to_rd_r[5])
  );
  X_BUF #(
    .LOC ( "IOB_X1Y37" ))
  ch1_to_rd_r_5_IBUF (
    .I(ch1_to_rd_r[5]),
    .O(\ch1_to_rd_r<5>/IBUF )
  );
  X_OPAD #(
    .LOC ( "IOB_X0Y30" ))
  \ch2_rd_i<14>/PAD  (
    .PAD(ch2_rd_i[14])
  );
  X_OBUF #(
    .LOC ( "IOB_X0Y30" ))
  ch2_rd_i_14_OBUF (
    .I(\ch2_to_rd_i<14>/IBUF ),
    .O(ch2_rd_i[14])
  );
  X_OPAD #(
    .LOC ( "IOB_X0Y15" ))
  \ch2_rd_r<2>/PAD  (
    .PAD(ch2_rd_r[2])
  );
  X_OBUF #(
    .LOC ( "IOB_X0Y15" ))
  ch2_rd_r_2_OBUF (
    .I(\ch2_to_rd_r<2>/IBUF ),
    .O(ch2_rd_r[2])
  );
  X_IPAD #(
    .LOC ( "IOB_X1Y103" ))
  \ch1_to_rd_r<6>/PAD  (
    .PAD(ch1_to_rd_r[6])
  );
  X_BUF #(
    .LOC ( "IOB_X1Y103" ))
  ch1_to_rd_r_6_IBUF (
    .I(ch1_to_rd_r[6]),
    .O(\ch1_to_rd_r<6>/IBUF )
  );
  X_OPAD #(
    .LOC ( "IOB_X1Y105" ))
  \ch2_rd_i<15>/PAD  (
    .PAD(ch2_rd_i[15])
  );
  X_OBUF #(
    .LOC ( "IOB_X1Y105" ))
  ch2_rd_i_15_OBUF (
    .I(\ch2_to_rd_i<15>/IBUF ),
    .O(ch2_rd_i[15])
  );
  X_OPAD #(
    .LOC ( "IOB_X0Y18" ))
  \ch2_rd_r<3>/PAD  (
    .PAD(ch2_rd_r[3])
  );
  X_OBUF #(
    .LOC ( "IOB_X0Y18" ))
  ch2_rd_r_3_OBUF (
    .I(\ch2_to_rd_r<3>/IBUF ),
    .O(ch2_rd_r[3])
  );
  X_IPAD #(
    .LOC ( "IOB_X0Y93" ))
  \ch1_to_rd_r<7>/PAD  (
    .PAD(ch1_to_rd_r[7])
  );
  X_BUF #(
    .LOC ( "IOB_X0Y93" ))
  ch1_to_rd_r_7_IBUF (
    .I(ch1_to_rd_r[7]),
    .O(\ch1_to_rd_r<7>/IBUF )
  );
  X_OPAD #(
    .LOC ( "IOB_X0Y26" ))
  \ch2_rd_r<4>/PAD  (
    .PAD(ch2_rd_r[4])
  );
  X_OBUF #(
    .LOC ( "IOB_X0Y26" ))
  ch2_rd_r_4_OBUF (
    .I(\ch2_to_rd_r<4>/IBUF ),
    .O(ch2_rd_r[4])
  );
  X_IPAD #(
    .LOC ( "IOB_X0Y108" ))
  \ch1_to_rd_r<8>/PAD  (
    .PAD(ch1_to_rd_r[8])
  );
  X_BUF #(
    .LOC ( "IOB_X0Y108" ))
  ch1_to_rd_r_8_IBUF (
    .I(ch1_to_rd_r[8]),
    .O(\ch1_to_rd_r<8>/IBUF )
  );
  X_IPAD #(
    .LOC ( "IOB_X0Y69" ))
  \addr_wr<0>/PAD  (
    .PAD(addr_wr[0])
  );
  X_BUF #(
    .LOC ( "IOB_X0Y69" ))
  \addr_wr<0>/IMUX  (
    .I(\addr_wr<0>/IBUF ),
    .O(addr_wr_0_IBUF_858)
  );
  X_BUF #(
    .LOC ( "IOB_X0Y69" ))
  addr_wr_0_IBUF (
    .I(addr_wr[0]),
    .O(\addr_wr<0>/IBUF )
  );
  X_OPAD #(
    .LOC ( "IOB_X0Y4" ))
  \ch2_rd_r<5>/PAD  (
    .PAD(ch2_rd_r[5])
  );
  X_OBUF #(
    .LOC ( "IOB_X0Y4" ))
  ch2_rd_r_5_OBUF (
    .I(\ch2_to_rd_r<5>/IBUF ),
    .O(ch2_rd_r[5])
  );
  X_IPAD #(
    .LOC ( "IOB_X0Y105" ))
  \ch1_to_rd_r<9>/PAD  (
    .PAD(ch1_to_rd_r[9])
  );
  X_BUF #(
    .LOC ( "IOB_X0Y105" ))
  ch1_to_rd_r_9_IBUF (
    .I(ch1_to_rd_r[9]),
    .O(\ch1_to_rd_r<9>/IBUF )
  );
  X_IPAD #(
    .LOC ( "IOB_X0Y75" ))
  \addr_wr<1>/PAD  (
    .PAD(addr_wr[1])
  );
  X_BUF #(
    .LOC ( "IOB_X0Y75" ))
  \addr_wr<1>/IMUX  (
    .I(\addr_wr<1>/IBUF ),
    .O(addr_wr_1_IBUF_860)
  );
  X_BUF #(
    .LOC ( "IOB_X0Y75" ))
  addr_wr_1_IBUF (
    .I(addr_wr[1]),
    .O(\addr_wr<1>/IBUF )
  );
  X_IPAD #(
    .LOC ( "IOB_X1Y39" ))
  \clk/PAD  (
    .PAD(clk)
  );
  X_BUF #(
    .LOC ( "IOB_X1Y39" ))
  \clk_BUFGP/IBUFG  (
    .I(clk),
    .O(\clk/IBUF )
  );
  X_OPAD #(
    .LOC ( "IOB_X0Y9" ))
  \ch2_rd_r<6>/PAD  (
    .PAD(ch2_rd_r[6])
  );
  X_OBUF #(
    .LOC ( "IOB_X0Y9" ))
  ch2_rd_r_6_OBUF (
    .I(\ch2_to_rd_r<6>/IBUF ),
    .O(ch2_rd_r[6])
  );
  X_IPAD #(
    .LOC ( "IOB_X0Y65" ))
  \addr_wr<2>/PAD  (
    .PAD(addr_wr[2])
  );
  X_BUF #(
    .LOC ( "IOB_X0Y65" ))
  \addr_wr<2>/IMUX  (
    .I(\addr_wr<2>/IBUF ),
    .O(addr_wr_2_IBUF_862)
  );
  X_BUF #(
    .LOC ( "IOB_X0Y65" ))
  addr_wr_2_IBUF (
    .I(addr_wr[2]),
    .O(\addr_wr<2>/IBUF )
  );
  X_OPAD #(
    .LOC ( "IOB_X0Y25" ))
  \ch2_rd_r<7>/PAD  (
    .PAD(ch2_rd_r[7])
  );
  X_OBUF #(
    .LOC ( "IOB_X0Y25" ))
  ch2_rd_r_7_OBUF (
    .I(\ch2_to_rd_r<7>/IBUF ),
    .O(ch2_rd_r[7])
  );
  X_IPAD #(
    .LOC ( "IOB_X0Y77" ))
  \addr_wr<3>/PAD  (
    .PAD(addr_wr[3])
  );
  X_BUF #(
    .LOC ( "IOB_X0Y77" ))
  \addr_wr<3>/IMUX  (
    .I(\addr_wr<3>/IBUF ),
    .O(addr_wr_3_IBUF_865)
  );
  X_BUF #(
    .LOC ( "IOB_X0Y77" ))
  addr_wr_3_IBUF (
    .I(addr_wr[3]),
    .O(\addr_wr<3>/IBUF )
  );
  X_OPAD #(
    .LOC ( "IOB_X0Y22" ))
  \ch2_rd_r<8>/PAD  (
    .PAD(ch2_rd_r[8])
  );
  X_OBUF #(
    .LOC ( "IOB_X0Y22" ))
  ch2_rd_r_8_OBUF (
    .I(\ch2_to_rd_r<8>/IBUF ),
    .O(ch2_rd_r[8])
  );
  X_IPAD #(
    .LOC ( "IOB_X0Y86" ))
  \addr_wr<4>/PAD  (
    .PAD(addr_wr[4])
  );
  X_BUF #(
    .LOC ( "IOB_X0Y86" ))
  \addr_wr<4>/IMUX  (
    .I(\addr_wr<4>/IBUF ),
    .O(addr_wr_4_IBUF_867)
  );
  X_BUF #(
    .LOC ( "IOB_X0Y86" ))
  addr_wr_4_IBUF (
    .I(addr_wr[4]),
    .O(\addr_wr<4>/IBUF )
  );
  X_OPAD #(
    .LOC ( "IOB_X0Y2" ))
  \ch2_rd_r<9>/PAD  (
    .PAD(ch2_rd_r[9])
  );
  X_OBUF #(
    .LOC ( "IOB_X0Y2" ))
  ch2_rd_r_9_OBUF (
    .I(\ch2_to_rd_r<9>/IBUF ),
    .O(ch2_rd_r[9])
  );
  X_IPAD #(
    .LOC ( "IOB_X0Y84" ))
  \addr_wr<5>/PAD  (
    .PAD(addr_wr[5])
  );
  X_BUF #(
    .LOC ( "IOB_X0Y84" ))
  \addr_wr<5>/IMUX  (
    .I(\addr_wr<5>/IBUF ),
    .O(addr_wr_5_IBUF_869)
  );
  X_BUF #(
    .LOC ( "IOB_X0Y84" ))
  addr_wr_5_IBUF (
    .I(addr_wr[5]),
    .O(\addr_wr<5>/IBUF )
  );
  X_IPAD #(
    .LOC ( "IOB_X0Y12" ))
  \ch2_to_rd_r<0>/PAD  (
    .PAD(ch2_to_rd_r[0])
  );
  X_BUF #(
    .LOC ( "IOB_X0Y12" ))
  ch2_to_rd_r_0_IBUF (
    .I(ch2_to_rd_r[0]),
    .O(\ch2_to_rd_r<0>/IBUF )
  );
  X_IPAD #(
    .LOC ( "IOB_X0Y83" ))
  \addr_wr<6>/PAD  (
    .PAD(addr_wr[6])
  );
  X_BUF #(
    .LOC ( "IOB_X0Y83" ))
  \addr_wr<6>/IMUX  (
    .I(\addr_wr<6>/IBUF ),
    .O(addr_wr_6_IBUF_871)
  );
  X_BUF #(
    .LOC ( "IOB_X0Y83" ))
  addr_wr_6_IBUF (
    .I(addr_wr[6]),
    .O(\addr_wr<6>/IBUF )
  );
  X_IPAD #(
    .LOC ( "IOB_X1Y36" ))
  \ch1_to_rd_i<0>/PAD  (
    .PAD(ch1_to_rd_i[0])
  );
  X_BUF #(
    .LOC ( "IOB_X1Y36" ))
  ch1_to_rd_i_0_IBUF (
    .I(ch1_to_rd_i[0]),
    .O(\ch1_to_rd_i<0>/IBUF )
  );
  X_IPAD #(
    .LOC ( "IOB_X0Y1" ))
  \ch2_to_rd_r<1>/PAD  (
    .PAD(ch2_to_rd_r[1])
  );
  X_BUF #(
    .LOC ( "IOB_X0Y1" ))
  ch2_to_rd_r_1_IBUF (
    .I(ch2_to_rd_r[1]),
    .O(\ch2_to_rd_r<1>/IBUF )
  );
  X_IPAD #(
    .LOC ( "IOB_X1Y113" ))
  \ch1_to_rd_r<10>/PAD  (
    .PAD(ch1_to_rd_r[10])
  );
  X_BUF #(
    .LOC ( "IOB_X1Y113" ))
  ch1_to_rd_r_10_IBUF (
    .I(ch1_to_rd_r[10]),
    .O(\ch1_to_rd_r<10>/IBUF )
  );
  X_IPAD #(
    .LOC ( "IOB_X0Y76" ))
  \addr_wr<7>/PAD  (
    .PAD(addr_wr[7])
  );
  X_BUF #(
    .LOC ( "IOB_X0Y76" ))
  \addr_wr<7>/IMUX  (
    .I(\addr_wr<7>/IBUF ),
    .O(addr_wr_7_IBUF_874)
  );
  X_BUF #(
    .LOC ( "IOB_X0Y76" ))
  addr_wr_7_IBUF (
    .I(addr_wr[7]),
    .O(\addr_wr<7>/IBUF )
  );
  X_IPAD #(
    .LOC ( "IOB_X1Y24" ))
  \ch1_to_rd_i<1>/PAD  (
    .PAD(ch1_to_rd_i[1])
  );
  X_BUF #(
    .LOC ( "IOB_X1Y24" ))
  ch1_to_rd_i_1_IBUF (
    .I(ch1_to_rd_i[1]),
    .O(\ch1_to_rd_i<1>/IBUF )
  );
  X_IPAD #(
    .LOC ( "IOB_X0Y14" ))
  \ch2_to_rd_r<2>/PAD  (
    .PAD(ch2_to_rd_r[2])
  );
  X_BUF #(
    .LOC ( "IOB_X0Y14" ))
  ch2_to_rd_r_2_IBUF (
    .I(ch2_to_rd_r[2]),
    .O(\ch2_to_rd_r<2>/IBUF )
  );
  X_IPAD #(
    .LOC ( "IOB_X0Y96" ))
  \ch1_to_rd_r<11>/PAD  (
    .PAD(ch1_to_rd_r[11])
  );
  X_BUF #(
    .LOC ( "IOB_X0Y96" ))
  ch1_to_rd_r_11_IBUF (
    .I(ch1_to_rd_r[11]),
    .O(\ch1_to_rd_r<11>/IBUF )
  );
  X_IPAD #(
    .LOC ( "IOB_X0Y78" ))
  \addr_wr<8>/PAD  (
    .PAD(addr_wr[8])
  );
  X_BUF #(
    .LOC ( "IOB_X0Y78" ))
  \addr_wr<8>/IMUX  (
    .I(\addr_wr<8>/IBUF ),
    .O(addr_wr_8_IBUF_876)
  );
  X_BUF #(
    .LOC ( "IOB_X0Y78" ))
  addr_wr_8_IBUF (
    .I(addr_wr[8]),
    .O(\addr_wr<8>/IBUF )
  );
  X_IPAD #(
    .LOC ( "IOB_X0Y64" ))
  \ch1_to_rd_i<2>/PAD  (
    .PAD(ch1_to_rd_i[2])
  );
  X_BUF #(
    .LOC ( "IOB_X0Y64" ))
  ch1_to_rd_i_2_IBUF (
    .I(ch1_to_rd_i[2]),
    .O(\ch1_to_rd_i<2>/IBUF )
  );
  X_IPAD #(
    .LOC ( "IOB_X0Y17" ))
  \ch2_to_rd_r<3>/PAD  (
    .PAD(ch2_to_rd_r[3])
  );
  X_BUF #(
    .LOC ( "IOB_X0Y17" ))
  ch2_to_rd_r_3_IBUF (
    .I(ch2_to_rd_r[3]),
    .O(\ch2_to_rd_r<3>/IBUF )
  );
  X_IPAD #(
    .LOC ( "IOB_X0Y46" ))
  \ch1_to_rd_r<12>/PAD  (
    .PAD(ch1_to_rd_r[12])
  );
  X_BUF #(
    .LOC ( "IOB_X0Y46" ))
  ch1_to_rd_r_12_IBUF (
    .I(ch1_to_rd_r[12]),
    .O(\ch1_to_rd_r<12>/IBUF )
  );
  X_IPAD #(
    .LOC ( "IOB_X0Y43" ))
  \ch1_to_rd_i<3>/PAD  (
    .PAD(ch1_to_rd_i[3])
  );
  X_BUF #(
    .LOC ( "IOB_X0Y43" ))
  ch1_to_rd_i_3_IBUF (
    .I(ch1_to_rd_i[3]),
    .O(\ch1_to_rd_i<3>/IBUF )
  );
  X_IPAD #(
    .LOC ( "IOB_X0Y27" ))
  \ch2_to_rd_r<4>/PAD  (
    .PAD(ch2_to_rd_r[4])
  );
  X_BUF #(
    .LOC ( "IOB_X0Y27" ))
  ch2_to_rd_r_4_IBUF (
    .I(ch2_to_rd_r[4]),
    .O(\ch2_to_rd_r<4>/IBUF )
  );
  X_IPAD #(
    .LOC ( "IOB_X0Y106" ))
  \ch1_to_rd_r<13>/PAD  (
    .PAD(ch1_to_rd_r[13])
  );
  X_BUF #(
    .LOC ( "IOB_X0Y106" ))
  ch1_to_rd_r_13_IBUF (
    .I(ch1_to_rd_r[13]),
    .O(\ch1_to_rd_r<13>/IBUF )
  );
  X_OPAD #(
    .LOC ( "IOB_X0Y109" ))
  \ch2_rd_i<0>/PAD  (
    .PAD(ch2_rd_i[0])
  );
  X_OBUF #(
    .LOC ( "IOB_X0Y109" ))
  ch2_rd_i_0_OBUF (
    .I(\ch2_to_rd_i<0>/IBUF ),
    .O(ch2_rd_i[0])
  );
  X_IPAD #(
    .LOC ( "IOB_X0Y45" ))
  \ch1_to_rd_i<4>/PAD  (
    .PAD(ch1_to_rd_i[4])
  );
  X_BUF #(
    .LOC ( "IOB_X0Y45" ))
  ch1_to_rd_i_4_IBUF (
    .I(ch1_to_rd_i[4]),
    .O(\ch1_to_rd_i<4>/IBUF )
  );
  X_IPAD #(
    .LOC ( "IOB_X0Y5" ))
  \ch2_to_rd_r<5>/PAD  (
    .PAD(ch2_to_rd_r[5])
  );
  X_BUF #(
    .LOC ( "IOB_X0Y5" ))
  ch2_to_rd_r_5_IBUF (
    .I(ch2_to_rd_r[5]),
    .O(\ch2_to_rd_r<5>/IBUF )
  );
  X_IPAD #(
    .LOC ( "IOB_X0Y49" ))
  \ch1_to_rd_r<14>/PAD  (
    .PAD(ch1_to_rd_r[14])
  );
  X_BUF #(
    .LOC ( "IOB_X0Y49" ))
  ch1_to_rd_r_14_IBUF (
    .I(ch1_to_rd_r[14]),
    .O(\ch1_to_rd_r<14>/IBUF )
  );
  X_OPAD #(
    .LOC ( "IOB_X0Y31" ))
  \ch2_rd_i<1>/PAD  (
    .PAD(ch2_rd_i[1])
  );
  X_OBUF #(
    .LOC ( "IOB_X0Y31" ))
  ch2_rd_i_1_OBUF (
    .I(\ch2_to_rd_i<1>/IBUF ),
    .O(ch2_rd_i[1])
  );
  X_IPAD #(
    .LOC ( "IOB_X0Y10" ))
  \ch1_to_rd_i<5>/PAD  (
    .PAD(ch1_to_rd_i[5])
  );
  X_BUF #(
    .LOC ( "IOB_X0Y10" ))
  ch1_to_rd_i_5_IBUF (
    .I(ch1_to_rd_i[5]),
    .O(\ch1_to_rd_i<5>/IBUF )
  );
  X_OPAD #(
    .LOC ( "IOB_X1Y112" ))
  \ch1_rd_r<10>/PAD  (
    .PAD(ch1_rd_r[10])
  );
  X_OBUF #(
    .LOC ( "IOB_X1Y112" ))
  ch1_rd_r_10_OBUF (
    .I(\ch1_to_rd_r<10>/IBUF ),
    .O(ch1_rd_r[10])
  );
  X_IPAD #(
    .LOC ( "IOB_X0Y8" ))
  \ch2_to_rd_r<6>/PAD  (
    .PAD(ch2_to_rd_r[6])
  );
  X_BUF #(
    .LOC ( "IOB_X0Y8" ))
  ch2_to_rd_r_6_IBUF (
    .I(ch2_to_rd_r[6]),
    .O(\ch2_to_rd_r<6>/IBUF )
  );
  X_IPAD #(
    .LOC ( "IOB_X0Y67" ))
  \ch1_to_rd_r<15>/PAD  (
    .PAD(ch1_to_rd_r[15])
  );
  X_BUF #(
    .LOC ( "IOB_X0Y67" ))
  ch1_to_rd_r_15_IBUF (
    .I(ch1_to_rd_r[15]),
    .O(\ch1_to_rd_r<15>/IBUF )
  );
  X_OPAD #(
    .LOC ( "IOB_X0Y88" ))
  \ch2_rd_i<2>/PAD  (
    .PAD(ch2_rd_i[2])
  );
  X_OBUF #(
    .LOC ( "IOB_X0Y88" ))
  ch2_rd_i_2_OBUF (
    .I(\ch2_to_rd_i<2>/IBUF ),
    .O(ch2_rd_i[2])
  );
  X_IPAD #(
    .LOC ( "IOB_X0Y72" ))
  \ch1_to_rd_i<6>/PAD  (
    .PAD(ch1_to_rd_i[6])
  );
  X_BUF #(
    .LOC ( "IOB_X0Y72" ))
  ch1_to_rd_i_6_IBUF (
    .I(ch1_to_rd_i[6]),
    .O(\ch1_to_rd_i<6>/IBUF )
  );
  X_OPAD #(
    .LOC ( "IOB_X0Y97" ))
  \ch1_rd_r<11>/PAD  (
    .PAD(ch1_rd_r[11])
  );
  X_OBUF #(
    .LOC ( "IOB_X0Y97" ))
  ch1_rd_r_11_OBUF (
    .I(\ch1_to_rd_r<11>/IBUF ),
    .O(ch1_rd_r[11])
  );
  X_IPAD #(
    .LOC ( "IOB_X0Y24" ))
  \ch2_to_rd_r<7>/PAD  (
    .PAD(ch2_to_rd_r[7])
  );
  X_BUF #(
    .LOC ( "IOB_X0Y24" ))
  ch2_to_rd_r_7_IBUF (
    .I(ch2_to_rd_r[7]),
    .O(\ch2_to_rd_r<7>/IBUF )
  );
  X_IPAD #(
    .LOC ( "IOB_X0Y52" ))
  \ch2_to_rd_i<10>/PAD  (
    .PAD(ch2_to_rd_i[10])
  );
  X_BUF #(
    .LOC ( "IOB_X0Y52" ))
  ch2_to_rd_i_10_IBUF (
    .I(ch2_to_rd_i[10]),
    .O(\ch2_to_rd_i<10>/IBUF )
  );
  X_OPAD #(
    .LOC ( "IOB_X0Y103" ))
  \ch2_rd_i<3>/PAD  (
    .PAD(ch2_rd_i[3])
  );
  X_OBUF #(
    .LOC ( "IOB_X0Y103" ))
  ch2_rd_i_3_OBUF (
    .I(\ch2_to_rd_i<3>/IBUF ),
    .O(ch2_rd_i[3])
  );
  X_IPAD #(
    .LOC ( "IOB_X1Y30" ))
  \ch1_to_rd_i<7>/PAD  (
    .PAD(ch1_to_rd_i[7])
  );
  X_BUF #(
    .LOC ( "IOB_X1Y30" ))
  ch1_to_rd_i_7_IBUF (
    .I(ch1_to_rd_i[7]),
    .O(\ch1_to_rd_i<7>/IBUF )
  );
  X_OPAD #(
    .LOC ( "IOB_X0Y54" ))
  \ch1_rd_r<12>/PAD  (
    .PAD(ch1_rd_r[12])
  );
  X_OBUF #(
    .LOC ( "IOB_X0Y54" ))
  ch1_rd_r_12_OBUF (
    .I(\ch1_to_rd_r<12>/IBUF ),
    .O(ch1_rd_r[12])
  );
  X_IPAD #(
    .LOC ( "IOB_X0Y23" ))
  \ch2_to_rd_r<8>/PAD  (
    .PAD(ch2_to_rd_r[8])
  );
  X_BUF #(
    .LOC ( "IOB_X0Y23" ))
  ch2_to_rd_r_8_IBUF (
    .I(ch2_to_rd_r[8]),
    .O(\ch2_to_rd_r<8>/IBUF )
  );
  X_IPAD #(
    .LOC ( "IOB_X0Y48" ))
  \ch2_to_rd_i<11>/PAD  (
    .PAD(ch2_to_rd_i[11])
  );
  X_BUF #(
    .LOC ( "IOB_X0Y48" ))
  ch2_to_rd_i_11_IBUF (
    .I(ch2_to_rd_i[11]),
    .O(\ch2_to_rd_i<11>/IBUF )
  );
  X_OPAD #(
    .LOC ( "IOB_X0Y110" ))
  \ch2_rd_i<4>/PAD  (
    .PAD(ch2_rd_i[4])
  );
  X_OBUF #(
    .LOC ( "IOB_X0Y110" ))
  ch2_rd_i_4_OBUF (
    .I(\ch2_to_rd_i<4>/IBUF ),
    .O(ch2_rd_i[4])
  );
  X_IPAD #(
    .LOC ( "IOB_X0Y42" ))
  \ch1_to_rd_i<8>/PAD  (
    .PAD(ch1_to_rd_i[8])
  );
  X_BUF #(
    .LOC ( "IOB_X0Y42" ))
  ch1_to_rd_i_8_IBUF (
    .I(ch1_to_rd_i[8]),
    .O(\ch1_to_rd_i<8>/IBUF )
  );
  X_OPAD #(
    .LOC ( "IOB_X0Y107" ))
  \ch1_rd_r<13>/PAD  (
    .PAD(ch1_rd_r[13])
  );
  X_OBUF #(
    .LOC ( "IOB_X0Y107" ))
  ch1_rd_r_13_OBUF (
    .I(\ch1_to_rd_r<13>/IBUF ),
    .O(ch1_rd_r[13])
  );
  X_IPAD #(
    .LOC ( "IOB_X0Y3" ))
  \ch2_to_rd_r<9>/PAD  (
    .PAD(ch2_to_rd_r[9])
  );
  X_BUF #(
    .LOC ( "IOB_X0Y3" ))
  ch2_to_rd_r_9_IBUF (
    .I(ch2_to_rd_r[9]),
    .O(\ch2_to_rd_r<9>/IBUF )
  );
  X_OPAD #(
    .LOC ( "IOB_X0Y20" ))
  \ch2_rd_r<10>/PAD  (
    .PAD(ch2_rd_r[10])
  );
  X_OBUF #(
    .LOC ( "IOB_X0Y20" ))
  ch2_rd_r_10_OBUF (
    .I(\ch2_to_rd_r<10>/IBUF ),
    .O(ch2_rd_r[10])
  );
  X_IPAD #(
    .LOC ( "IOB_X0Y90" ))
  \ch2_to_rd_i<12>/PAD  (
    .PAD(ch2_to_rd_i[12])
  );
  X_BUF #(
    .LOC ( "IOB_X0Y90" ))
  ch2_to_rd_i_12_IBUF (
    .I(ch2_to_rd_i[12]),
    .O(\ch2_to_rd_i<12>/IBUF )
  );
  X_OPAD #(
    .LOC ( "IOB_X1Y119" ))
  \ch2_rd_i<5>/PAD  (
    .PAD(ch2_rd_i[5])
  );
  X_OBUF #(
    .LOC ( "IOB_X1Y119" ))
  ch2_rd_i_5_OBUF (
    .I(\ch2_to_rd_i<5>/IBUF ),
    .O(ch2_rd_i[5])
  );
  X_IPAD #(
    .LOC ( "IOB_X1Y33" ))
  \ch1_to_rd_i<9>/PAD  (
    .PAD(ch1_to_rd_i[9])
  );
  X_BUF #(
    .LOC ( "IOB_X1Y33" ))
  ch1_to_rd_i_9_IBUF (
    .I(ch1_to_rd_i[9]),
    .O(\ch1_to_rd_i<9>/IBUF )
  );
  X_OPAD #(
    .LOC ( "IOB_X0Y50" ))
  \ch1_rd_r<14>/PAD  (
    .PAD(ch1_rd_r[14])
  );
  X_OBUF #(
    .LOC ( "IOB_X0Y50" ))
  ch1_rd_r_14_OBUF (
    .I(\ch1_to_rd_r<14>/IBUF ),
    .O(ch1_rd_r[14])
  );
  X_OPAD #(
    .LOC ( "IOB_X0Y7" ))
  \ch2_rd_r<11>/PAD  (
    .PAD(ch2_rd_r[11])
  );
  X_OBUF #(
    .LOC ( "IOB_X0Y7" ))
  ch2_rd_r_11_OBUF (
    .I(\ch2_to_rd_r<11>/IBUF ),
    .O(ch2_rd_r[11])
  );
  X_IPAD #(
    .LOC ( "IOB_X1Y111" ))
  \ch2_to_rd_i<13>/PAD  (
    .PAD(ch2_to_rd_i[13])
  );
  X_BUF #(
    .LOC ( "IOB_X1Y111" ))
  ch2_to_rd_i_13_IBUF (
    .I(ch2_to_rd_i[13]),
    .O(\ch2_to_rd_i<13>/IBUF )
  );
  X_OPAD #(
    .LOC ( "IOB_X0Y70" ))
  \ch2_rd_i<6>/PAD  (
    .PAD(ch2_rd_i[6])
  );
  X_OBUF #(
    .LOC ( "IOB_X0Y70" ))
  ch2_rd_i_6_OBUF (
    .I(\ch2_to_rd_i<6>/IBUF ),
    .O(ch2_rd_i[6])
  );
  X_OPAD #(
    .LOC ( "IOB_X0Y66" ))
  \ch1_rd_r<15>/PAD  (
    .PAD(ch1_rd_r[15])
  );
  X_OBUF #(
    .LOC ( "IOB_X0Y66" ))
  ch1_rd_r_15_OBUF (
    .I(\ch1_to_rd_r<15>/IBUF ),
    .O(ch1_rd_r[15])
  );
  X_OPAD #(
    .LOC ( "IOB_X1Y21" ))
  \ch2_rd_r<12>/PAD  (
    .PAD(ch2_rd_r[12])
  );
  X_OBUF #(
    .LOC ( "IOB_X1Y21" ))
  ch2_rd_r_12_OBUF (
    .I(\ch2_to_rd_r<12>/IBUF ),
    .O(ch2_rd_r[12])
  );
  X_IPAD #(
    .LOC ( "IOB_X0Y29" ))
  \ch2_to_rd_i<14>/PAD  (
    .PAD(ch2_to_rd_i[14])
  );
  X_BUF #(
    .LOC ( "IOB_X0Y29" ))
  ch2_to_rd_i_14_IBUF (
    .I(ch2_to_rd_i[14]),
    .O(\ch2_to_rd_i<14>/IBUF )
  );
  X_OPAD #(
    .LOC ( "IOB_X1Y42" ))
  \ch2_rd_i<7>/PAD  (
    .PAD(ch2_rd_i[7])
  );
  X_OBUF #(
    .LOC ( "IOB_X1Y42" ))
  ch2_rd_i_7_OBUF (
    .I(\ch2_to_rd_i<7>/IBUF ),
    .O(ch2_rd_i[7])
  );
  X_OPAD #(
    .LOC ( "IOB_X1Y25" ))
  \ch2_rd_r<13>/PAD  (
    .PAD(ch2_rd_r[13])
  );
  X_OBUF #(
    .LOC ( "IOB_X1Y25" ))
  ch2_rd_r_13_OBUF (
    .I(\ch2_to_rd_r<13>/IBUF ),
    .O(ch2_rd_r[13])
  );
  X_IPAD #(
    .LOC ( "IOB_X1Y104" ))
  \ch2_to_rd_i<15>/PAD  (
    .PAD(ch2_to_rd_i[15])
  );
  X_BUF #(
    .LOC ( "IOB_X1Y104" ))
  ch2_to_rd_i_15_IBUF (
    .I(ch2_to_rd_i[15]),
    .O(\ch2_to_rd_i<15>/IBUF )
  );
  X_OPAD #(
    .LOC ( "IOB_X0Y58" ))
  \ch2_rd_i<8>/PAD  (
    .PAD(ch2_rd_i[8])
  );
  X_OBUF #(
    .LOC ( "IOB_X0Y58" ))
  ch2_rd_i_8_OBUF (
    .I(\ch2_to_rd_i<8>/IBUF ),
    .O(ch2_rd_i[8])
  );
  X_OPAD #(
    .LOC ( "IOB_X1Y40" ))
  \ch2_rd_r<14>/PAD  (
    .PAD(ch2_rd_r[14])
  );
  X_OBUF #(
    .LOC ( "IOB_X1Y40" ))
  ch2_rd_r_14_OBUF (
    .I(\ch2_to_rd_r<14>/IBUF ),
    .O(ch2_rd_r[14])
  );
  X_OPAD #(
    .LOC ( "IOB_X0Y99" ))
  \ch2_rd_i<9>/PAD  (
    .PAD(ch2_rd_i[9])
  );
  X_OBUF #(
    .LOC ( "IOB_X0Y99" ))
  ch2_rd_i_9_OBUF (
    .I(\ch2_to_rd_i<9>/IBUF ),
    .O(ch2_rd_i[9])
  );
  X_OPAD #(
    .LOC ( "IOB_X0Y113" ))
  \ch1_rd_r<0>/PAD  (
    .PAD(ch1_rd_r[0])
  );
  X_OBUF #(
    .LOC ( "IOB_X0Y113" ))
  ch1_rd_r_0_OBUF (
    .I(\ch1_to_rd_r<0>/IBUF ),
    .O(ch1_rd_r[0])
  );
  X_OPAD #(
    .LOC ( "IOB_X0Y13" ))
  \ch2_rd_r<15>/PAD  (
    .PAD(ch2_rd_r[15])
  );
  X_OBUF #(
    .LOC ( "IOB_X0Y13" ))
  ch2_rd_r_15_OBUF (
    .I(\ch2_to_rd_r<15>/IBUF ),
    .O(ch2_rd_r[15])
  );
  X_IPAD #(
    .LOC ( "IOB_X0Y100" ))
  \ch2_to_rd_i<0>/PAD  (
    .PAD(ch2_to_rd_i[0])
  );
  X_BUF #(
    .LOC ( "IOB_X0Y100" ))
  ch2_to_rd_i_0_IBUF (
    .I(ch2_to_rd_i[0]),
    .O(\ch2_to_rd_i<0>/IBUF )
  );
  X_OPAD #(
    .LOC ( "IOB_X1Y114" ))
  \ch1_rd_r<1>/PAD  (
    .PAD(ch1_rd_r[1])
  );
  X_OBUF #(
    .LOC ( "IOB_X1Y114" ))
  ch1_rd_r_1_OBUF (
    .I(\ch1_to_rd_r<1>/IBUF ),
    .O(ch1_rd_r[1])
  );
  X_IPAD #(
    .LOC ( "IOB_X0Y40" ))
  \ch2_to_rd_i<1>/PAD  (
    .PAD(ch2_to_rd_i[1])
  );
  X_BUF #(
    .LOC ( "IOB_X0Y40" ))
  ch2_to_rd_i_1_IBUF (
    .I(ch2_to_rd_i[1]),
    .O(\ch2_to_rd_i<1>/IBUF )
  );
  X_OPAD #(
    .LOC ( "IOB_X1Y108" ))
  \ch1_rd_r<2>/PAD  (
    .PAD(ch1_rd_r[2])
  );
  X_OBUF #(
    .LOC ( "IOB_X1Y108" ))
  ch1_rd_r_2_OBUF (
    .I(\ch1_to_rd_r<2>/IBUF ),
    .O(ch1_rd_r[2])
  );
  X_IPAD #(
    .LOC ( "IOB_X0Y85" ))
  \ch2_to_rd_i<2>/PAD  (
    .PAD(ch2_to_rd_i[2])
  );
  X_BUF #(
    .LOC ( "IOB_X0Y85" ))
  ch2_to_rd_i_2_IBUF (
    .I(ch2_to_rd_i[2]),
    .O(\ch2_to_rd_i<2>/IBUF )
  );
  X_OPAD #(
    .LOC ( "IOB_X1Y56" ))
  \ch1_rd_r<3>/PAD  (
    .PAD(ch1_rd_r[3])
  );
  X_OBUF #(
    .LOC ( "IOB_X1Y56" ))
  ch1_rd_r_3_OBUF (
    .I(\ch1_to_rd_r<3>/IBUF ),
    .O(ch1_rd_r[3])
  );
  X_IPAD #(
    .LOC ( "IOB_X0Y102" ))
  \ch2_to_rd_i<3>/PAD  (
    .PAD(ch2_to_rd_i[3])
  );
  X_BUF #(
    .LOC ( "IOB_X0Y102" ))
  ch2_to_rd_i_3_IBUF (
    .I(ch2_to_rd_i[3]),
    .O(\ch2_to_rd_i<3>/IBUF )
  );
  X_OPAD #(
    .LOC ( "IOB_X0Y61" ))
  \ch1_rd_r<4>/PAD  (
    .PAD(ch1_rd_r[4])
  );
  X_OBUF #(
    .LOC ( "IOB_X0Y61" ))
  ch1_rd_r_4_OBUF (
    .I(\ch1_to_rd_r<4>/IBUF ),
    .O(ch1_rd_r[4])
  );
  X_IPAD #(
    .LOC ( "IOB_X0Y111" ))
  \ch2_to_rd_i<4>/PAD  (
    .PAD(ch2_to_rd_i[4])
  );
  X_BUF #(
    .LOC ( "IOB_X0Y111" ))
  ch2_to_rd_i_4_IBUF (
    .I(ch2_to_rd_i[4]),
    .O(\ch2_to_rd_i<4>/IBUF )
  );
  X_OPAD #(
    .LOC ( "IOB_X1Y34" ))
  \ch1_rd_r<5>/PAD  (
    .PAD(ch1_rd_r[5])
  );
  X_OBUF #(
    .LOC ( "IOB_X1Y34" ))
  ch1_rd_r_5_OBUF (
    .I(\ch1_to_rd_r<5>/IBUF ),
    .O(ch1_rd_r[5])
  );
  X_IPAD #(
    .LOC ( "IOB_X1Y118" ))
  \ch2_to_rd_i<5>/PAD  (
    .PAD(ch2_to_rd_i[5])
  );
  X_BUF #(
    .LOC ( "IOB_X1Y118" ))
  ch2_to_rd_i_5_IBUF (
    .I(ch2_to_rd_i[5]),
    .O(\ch2_to_rd_i<5>/IBUF )
  );
  X_OPAD #(
    .LOC ( "IOB_X1Y102" ))
  \ch1_rd_r<6>/PAD  (
    .PAD(ch1_rd_r[6])
  );
  X_OBUF #(
    .LOC ( "IOB_X1Y102" ))
  ch1_rd_r_6_OBUF (
    .I(\ch1_to_rd_r<6>/IBUF ),
    .O(ch1_rd_r[6])
  );
  X_IPAD #(
    .LOC ( "IOB_X0Y71" ))
  \ch2_to_rd_i<6>/PAD  (
    .PAD(ch2_to_rd_i[6])
  );
  X_BUF #(
    .LOC ( "IOB_X0Y71" ))
  ch2_to_rd_i_6_IBUF (
    .I(ch2_to_rd_i[6]),
    .O(\ch2_to_rd_i<6>/IBUF )
  );
  X_OPAD #(
    .LOC ( "IOB_X0Y95" ))
  \ch1_rd_r<7>/PAD  (
    .PAD(ch1_rd_r[7])
  );
  X_OBUF #(
    .LOC ( "IOB_X0Y95" ))
  ch1_rd_r_7_OBUF (
    .I(\ch1_to_rd_r<7>/IBUF ),
    .O(ch1_rd_r[7])
  );
  X_IPAD #(
    .LOC ( "IOB_X1Y44" ))
  \ch2_to_rd_i<7>/PAD  (
    .PAD(ch2_to_rd_i[7])
  );
  X_BUF #(
    .LOC ( "IOB_X1Y44" ))
  ch2_to_rd_i_7_IBUF (
    .I(ch2_to_rd_i[7]),
    .O(\ch2_to_rd_i<7>/IBUF )
  );
  X_OPAD #(
    .LOC ( "IOB_X0Y112" ))
  \ch1_rd_r<8>/PAD  (
    .PAD(ch1_rd_r[8])
  );
  X_OBUF #(
    .LOC ( "IOB_X0Y112" ))
  ch1_rd_r_8_OBUF (
    .I(\ch1_to_rd_r<8>/IBUF ),
    .O(ch1_rd_r[8])
  );
  X_IPAD #(
    .LOC ( "IOB_X0Y57" ))
  \ch2_to_rd_i<8>/PAD  (
    .PAD(ch2_to_rd_i[8])
  );
  X_BUF #(
    .LOC ( "IOB_X0Y57" ))
  ch2_to_rd_i_8_IBUF (
    .I(ch2_to_rd_i[8]),
    .O(\ch2_to_rd_i<8>/IBUF )
  );
  X_OPAD #(
    .LOC ( "IOB_X0Y104" ))
  \ch1_rd_r<9>/PAD  (
    .PAD(ch1_rd_r[9])
  );
  X_OBUF #(
    .LOC ( "IOB_X0Y104" ))
  ch1_rd_r_9_OBUF (
    .I(\ch1_to_rd_r<9>/IBUF ),
    .O(ch1_rd_r[9])
  );
  X_IPAD #(
    .LOC ( "IOB_X0Y98" ))
  \ch2_to_rd_i<9>/PAD  (
    .PAD(ch2_to_rd_i[9])
  );
  X_BUF #(
    .LOC ( "IOB_X0Y98" ))
  ch2_to_rd_i_9_IBUF (
    .I(ch2_to_rd_i[9]),
    .O(\ch2_to_rd_i<9>/IBUF )
  );
  X_OPAD #(
    .LOC ( "IOB_X1Y55" ))
  \addr_rd_ch1<0>/PAD  (
    .PAD(addr_rd_ch1[0])
  );
  X_OBUF #(
    .LOC ( "IOB_X1Y55" ))
  addr_rd_ch1_0_OBUF (
    .I(addr_rd_ch1_0_949),
    .O(addr_rd_ch1[0])
  );
  X_OPAD #(
    .LOC ( "IOB_X0Y55" ))
  \addr_rd_ch1<1>/PAD  (
    .PAD(addr_rd_ch1[1])
  );
  X_OBUF #(
    .LOC ( "IOB_X0Y55" ))
  addr_rd_ch1_1_OBUF (
    .I(addr_rd_ch1_1_950),
    .O(addr_rd_ch1[1])
  );
  X_OPAD #(
    .LOC ( "IOB_X1Y54" ))
  \addr_rd_ch1<2>/PAD  (
    .PAD(addr_rd_ch1[2])
  );
  X_OBUF #(
    .LOC ( "IOB_X1Y54" ))
  addr_rd_ch1_2_OBUF (
    .I(addr_rd_ch1_2_951),
    .O(addr_rd_ch1[2])
  );
  X_OPAD #(
    .LOC ( "IOB_X1Y59" ))
  \addr_rd_ch1<3>/PAD  (
    .PAD(addr_rd_ch1[3])
  );
  X_OBUF #(
    .LOC ( "IOB_X1Y59" ))
  addr_rd_ch1_3_OBUF (
    .I(addr_rd_ch1_3_952),
    .O(addr_rd_ch1[3])
  );
  X_OPAD #(
    .LOC ( "IOB_X0Y59" ))
  \addr_rd_ch2<0>/PAD  (
    .PAD(addr_rd_ch2[0])
  );
  X_OBUF #(
    .LOC ( "IOB_X0Y59" ))
  addr_rd_ch2_0_OBUF (
    .I(addr_rd_ch2_0_953),
    .O(addr_rd_ch2[0])
  );
  X_OPAD #(
    .LOC ( "IOB_X0Y81" ))
  \addr_rd_ch1<4>/PAD  (
    .PAD(addr_rd_ch1[4])
  );
  X_OBUF #(
    .LOC ( "IOB_X0Y81" ))
  addr_rd_ch1_4_OBUF (
    .I(addr_rd_ch1_4_954),
    .O(addr_rd_ch1[4])
  );
  X_OPAD #(
    .LOC ( "IOB_X1Y31" ))
  \ch1_rd_i<0>/PAD  (
    .PAD(ch1_rd_i[0])
  );
  X_OBUF #(
    .LOC ( "IOB_X1Y31" ))
  ch1_rd_i_0_OBUF (
    .I(\ch1_to_rd_i<0>/IBUF ),
    .O(ch1_rd_i[0])
  );
  X_OPAD #(
    .LOC ( "IOB_X0Y63" ))
  \addr_rd_ch2<1>/PAD  (
    .PAD(addr_rd_ch2[1])
  );
  X_OBUF #(
    .LOC ( "IOB_X0Y63" ))
  addr_rd_ch2_1_OBUF (
    .I(addr_rd_ch2_1_955),
    .O(addr_rd_ch2[1])
  );
  X_OPAD #(
    .LOC ( "IOB_X0Y68" ))
  \addr_rd_ch1<5>/PAD  (
    .PAD(addr_rd_ch1[5])
  );
  X_OBUF #(
    .LOC ( "IOB_X0Y68" ))
  addr_rd_ch1_5_OBUF (
    .I(addr_rd_ch1_5_956),
    .O(addr_rd_ch1[5])
  );
  X_IPAD #(
    .LOC ( "IOB_X0Y21" ))
  \ch2_to_rd_r<10>/PAD  (
    .PAD(ch2_to_rd_r[10])
  );
  X_BUF #(
    .LOC ( "IOB_X0Y21" ))
  ch2_to_rd_r_10_IBUF (
    .I(ch2_to_rd_r[10]),
    .O(\ch2_to_rd_r<10>/IBUF )
  );
  X_OPAD #(
    .LOC ( "IOB_X1Y27" ))
  \ch1_rd_i<1>/PAD  (
    .PAD(ch1_rd_i[1])
  );
  X_OBUF #(
    .LOC ( "IOB_X1Y27" ))
  ch1_rd_i_1_OBUF (
    .I(\ch1_to_rd_i<1>/IBUF ),
    .O(ch1_rd_i[1])
  );
  X_OPAD #(
    .LOC ( "IOB_X1Y57" ))
  \addr_rd_ch2<2>/PAD  (
    .PAD(addr_rd_ch2[2])
  );
  X_OBUF #(
    .LOC ( "IOB_X1Y57" ))
  addr_rd_ch2_2_OBUF (
    .I(addr_rd_ch2_2_957),
    .O(addr_rd_ch2[2])
  );
  X_OPAD #(
    .LOC ( "IOB_X0Y94" ))
  \addr_rd_ch1<6>/PAD  (
    .PAD(addr_rd_ch1[6])
  );
  X_OBUF #(
    .LOC ( "IOB_X0Y94" ))
  addr_rd_ch1_6_OBUF (
    .I(addr_rd_ch1_6_958),
    .O(addr_rd_ch1[6])
  );
  X_IPAD #(
    .LOC ( "IOB_X0Y6" ))
  \ch2_to_rd_r<11>/PAD  (
    .PAD(ch2_to_rd_r[11])
  );
  X_BUF #(
    .LOC ( "IOB_X0Y6" ))
  ch2_to_rd_r_11_IBUF (
    .I(ch2_to_rd_r[11]),
    .O(\ch2_to_rd_r<11>/IBUF )
  );
  X_IPAD #(
    .LOC ( "IOB_X1Y43" ))
  \ch1_to_rd_i<10>/PAD  (
    .PAD(ch1_to_rd_i[10])
  );
  X_BUF #(
    .LOC ( "IOB_X1Y43" ))
  ch1_to_rd_i_10_IBUF (
    .I(ch1_to_rd_i[10]),
    .O(\ch1_to_rd_i<10>/IBUF )
  );
  X_OPAD #(
    .LOC ( "IOB_X0Y62" ))
  \ch1_rd_i<2>/PAD  (
    .PAD(ch1_rd_i[2])
  );
  X_OBUF #(
    .LOC ( "IOB_X0Y62" ))
  ch1_rd_i_2_OBUF (
    .I(\ch1_to_rd_i<2>/IBUF ),
    .O(ch1_rd_i[2])
  );
  X_OPAD #(
    .LOC ( "IOB_X0Y47" ))
  \addr_rd_ch2<3>/PAD  (
    .PAD(addr_rd_ch2[3])
  );
  X_OBUF #(
    .LOC ( "IOB_X0Y47" ))
  addr_rd_ch2_3_OBUF (
    .I(addr_rd_ch2_3_960),
    .O(addr_rd_ch2[3])
  );
  X_OPAD #(
    .LOC ( "IOB_X0Y79" ))
  \addr_rd_ch1<7>/PAD  (
    .PAD(addr_rd_ch1[7])
  );
  X_OBUF #(
    .LOC ( "IOB_X0Y79" ))
  addr_rd_ch1_7_OBUF (
    .I(addr_rd_ch1_7_961),
    .O(addr_rd_ch1[7])
  );
  X_IPAD #(
    .LOC ( "IOB_X1Y20" ))
  \ch2_to_rd_r<12>/PAD  (
    .PAD(ch2_to_rd_r[12])
  );
  X_BUF #(
    .LOC ( "IOB_X1Y20" ))
  ch2_to_rd_r_12_IBUF (
    .I(ch2_to_rd_r[12]),
    .O(\ch2_to_rd_r<12>/IBUF )
  );
  X_IPAD #(
    .LOC ( "IOB_X1Y35" ))
  \ch1_to_rd_i<11>/PAD  (
    .PAD(ch1_to_rd_i[11])
  );
  X_BUF #(
    .LOC ( "IOB_X1Y35" ))
  ch1_to_rd_i_11_IBUF (
    .I(ch1_to_rd_i[11]),
    .O(\ch1_to_rd_i<11>/IBUF )
  );
  X_OPAD #(
    .LOC ( "IOB_X0Y41" ))
  \ch1_rd_i<3>/PAD  (
    .PAD(ch1_rd_i[3])
  );
  X_OBUF #(
    .LOC ( "IOB_X0Y41" ))
  ch1_rd_i_3_OBUF (
    .I(\ch1_to_rd_i<3>/IBUF ),
    .O(ch1_rd_i[3])
  );
  X_OPAD #(
    .LOC ( "IOB_X0Y89" ))
  \addr_rd_ch2<4>/PAD  (
    .PAD(addr_rd_ch2[4])
  );
  X_OBUF #(
    .LOC ( "IOB_X0Y89" ))
  addr_rd_ch2_4_OBUF (
    .I(addr_rd_ch2_4_963),
    .O(addr_rd_ch2[4])
  );
  X_OPAD #(
    .LOC ( "IOB_X0Y74" ))
  \addr_rd_ch1<8>/PAD  (
    .PAD(addr_rd_ch1[8])
  );
  X_OBUF #(
    .LOC ( "IOB_X0Y74" ))
  addr_rd_ch1_8_OBUF (
    .I(addr_rd_ch1_8_964),
    .O(addr_rd_ch1[8])
  );
  X_IPAD #(
    .LOC ( "IOB_X1Y22" ))
  \ch2_to_rd_r<13>/PAD  (
    .PAD(ch2_to_rd_r[13])
  );
  X_BUF #(
    .LOC ( "IOB_X1Y22" ))
  ch2_to_rd_r_13_IBUF (
    .I(ch2_to_rd_r[13]),
    .O(\ch2_to_rd_r<13>/IBUF )
  );
  X_IPAD #(
    .LOC ( "IOB_X1Y29" ))
  \ch1_to_rd_i<12>/PAD  (
    .PAD(ch1_to_rd_i[12])
  );
  X_BUF #(
    .LOC ( "IOB_X1Y29" ))
  ch1_to_rd_i_12_IBUF (
    .I(ch1_to_rd_i[12]),
    .O(\ch1_to_rd_i<12>/IBUF )
  );
  X_OPAD #(
    .LOC ( "IOB_X0Y44" ))
  \ch1_rd_i<4>/PAD  (
    .PAD(ch1_rd_i[4])
  );
  X_OBUF #(
    .LOC ( "IOB_X0Y44" ))
  ch1_rd_i_4_OBUF (
    .I(\ch1_to_rd_i<4>/IBUF ),
    .O(ch1_rd_i[4])
  );
  X_OPAD #(
    .LOC ( "IOB_X0Y82" ))
  \addr_rd_ch2<5>/PAD  (
    .PAD(addr_rd_ch2[5])
  );
  X_OBUF #(
    .LOC ( "IOB_X0Y82" ))
  addr_rd_ch2_5_OBUF (
    .I(addr_rd_ch2_5_966),
    .O(addr_rd_ch2[5])
  );
  X_IPAD #(
    .LOC ( "IOB_X1Y45" ))
  \ch2_to_rd_r<14>/PAD  (
    .PAD(ch2_to_rd_r[14])
  );
  X_BUF #(
    .LOC ( "IOB_X1Y45" ))
  ch2_to_rd_r_14_IBUF (
    .I(ch2_to_rd_r[14]),
    .O(\ch2_to_rd_r<14>/IBUF )
  );
  X_IPAD #(
    .LOC ( "IOB_X1Y47" ))
  \ch1_to_rd_i<13>/PAD  (
    .PAD(ch1_to_rd_i[13])
  );
  X_BUF #(
    .LOC ( "IOB_X1Y47" ))
  ch1_to_rd_i_13_IBUF (
    .I(ch1_to_rd_i[13]),
    .O(\ch1_to_rd_i<13>/IBUF )
  );
  X_OPAD #(
    .LOC ( "IOB_X0Y19" ))
  \ch1_rd_i<5>/PAD  (
    .PAD(ch1_rd_i[5])
  );
  X_OBUF #(
    .LOC ( "IOB_X0Y19" ))
  ch1_rd_i_5_OBUF (
    .I(\ch1_to_rd_i<5>/IBUF ),
    .O(ch1_rd_i[5])
  );
  X_OPAD #(
    .LOC ( "IOB_X0Y80" ))
  \addr_rd_ch2<6>/PAD  (
    .PAD(addr_rd_ch2[6])
  );
  X_OBUF #(
    .LOC ( "IOB_X0Y80" ))
  addr_rd_ch2_6_OBUF (
    .I(addr_rd_ch2_6_969),
    .O(addr_rd_ch2[6])
  );
  X_IPAD #(
    .LOC ( "IOB_X0Y16" ))
  \ch2_to_rd_r<15>/PAD  (
    .PAD(ch2_to_rd_r[15])
  );
  X_BUF #(
    .LOC ( "IOB_X0Y16" ))
  ch2_to_rd_r_15_IBUF (
    .I(ch2_to_rd_r[15]),
    .O(\ch2_to_rd_r<15>/IBUF )
  );
  X_IPAD #(
    .LOC ( "IOB_X0Y115" ))
  \ch1_to_rd_i<14>/PAD  (
    .PAD(ch1_to_rd_i[14])
  );
  X_BUF #(
    .LOC ( "IOB_X0Y115" ))
  ch1_to_rd_i_14_IBUF (
    .I(ch1_to_rd_i[14]),
    .O(\ch1_to_rd_i<14>/IBUF )
  );
  X_OPAD #(
    .LOC ( "IOB_X0Y73" ))
  \ch1_rd_i<6>/PAD  (
    .PAD(ch1_rd_i[6])
  );
  X_OBUF #(
    .LOC ( "IOB_X0Y73" ))
  ch1_rd_i_6_OBUF (
    .I(\ch1_to_rd_i<6>/IBUF ),
    .O(ch1_rd_i[6])
  );
  X_OPAD #(
    .LOC ( "IOB_X1Y41" ))
  \ch1_rd_i<10>/PAD  (
    .PAD(ch1_rd_i[10])
  );
  X_OBUF #(
    .LOC ( "IOB_X1Y41" ))
  ch1_rd_i_10_OBUF (
    .I(\ch1_to_rd_i<10>/IBUF ),
    .O(ch1_rd_i[10])
  );
  X_OPAD #(
    .LOC ( "IOB_X0Y92" ))
  \addr_rd_ch2<7>/PAD  (
    .PAD(addr_rd_ch2[7])
  );
  X_OBUF #(
    .LOC ( "IOB_X0Y92" ))
  addr_rd_ch2_7_OBUF (
    .I(addr_rd_ch2_7_971),
    .O(addr_rd_ch2[7])
  );
  X_IPAD #(
    .LOC ( "IOB_X1Y50" ))
  \ch1_to_rd_i<15>/PAD  (
    .PAD(ch1_to_rd_i[15])
  );
  X_BUF #(
    .LOC ( "IOB_X1Y50" ))
  ch1_to_rd_i_15_IBUF (
    .I(ch1_to_rd_i[15]),
    .O(\ch1_to_rd_i<15>/IBUF )
  );
  X_OPAD #(
    .LOC ( "IOB_X1Y26" ))
  \ch1_rd_i<7>/PAD  (
    .PAD(ch1_rd_i[7])
  );
  X_OBUF #(
    .LOC ( "IOB_X1Y26" ))
  ch1_rd_i_7_OBUF (
    .I(\ch1_to_rd_i<7>/IBUF ),
    .O(ch1_rd_i[7])
  );
  X_OPAD #(
    .LOC ( "IOB_X1Y23" ))
  \ch1_rd_i<11>/PAD  (
    .PAD(ch1_rd_i[11])
  );
  X_OBUF #(
    .LOC ( "IOB_X1Y23" ))
  ch1_rd_i_11_OBUF (
    .I(\ch1_to_rd_i<11>/IBUF ),
    .O(ch1_rd_i[11])
  );
  X_OPAD #(
    .LOC ( "IOB_X0Y87" ))
  \addr_rd_ch2<8>/PAD  (
    .PAD(addr_rd_ch2[8])
  );
  X_OBUF #(
    .LOC ( "IOB_X0Y87" ))
  addr_rd_ch2_8_OBUF (
    .I(addr_rd_ch2_8_973),
    .O(addr_rd_ch2[8])
  );
  X_OPAD #(
    .LOC ( "IOB_X1Y48" ))
  \ch1_rd_i<8>/PAD  (
    .PAD(ch1_rd_i[8])
  );
  X_OBUF #(
    .LOC ( "IOB_X1Y48" ))
  ch1_rd_i_8_OBUF (
    .I(\ch1_to_rd_i<8>/IBUF ),
    .O(ch1_rd_i[8])
  );
  X_IPAD #(
    .LOC ( "IOB_X0Y114" ))
  \ch1_to_rd_r<0>/PAD  (
    .PAD(ch1_to_rd_r[0])
  );
  X_BUF #(
    .LOC ( "IOB_X0Y114" ))
  ch1_to_rd_r_0_IBUF (
    .I(ch1_to_rd_r[0]),
    .O(\ch1_to_rd_r<0>/IBUF )
  );
  X_OPAD #(
    .LOC ( "IOB_X1Y28" ))
  \ch1_rd_i<12>/PAD  (
    .PAD(ch1_rd_i[12])
  );
  X_OBUF #(
    .LOC ( "IOB_X1Y28" ))
  ch1_rd_i_12_OBUF (
    .I(\ch1_to_rd_i<12>/IBUF ),
    .O(ch1_rd_i[12])
  );
  X_OPAD #(
    .LOC ( "IOB_X1Y32" ))
  \ch1_rd_i<9>/PAD  (
    .PAD(ch1_rd_i[9])
  );
  X_OBUF #(
    .LOC ( "IOB_X1Y32" ))
  ch1_rd_i_9_OBUF (
    .I(\ch1_to_rd_i<9>/IBUF ),
    .O(ch1_rd_i[9])
  );
  X_IPAD #(
    .LOC ( "IOB_X1Y58" ))
  \rst/PAD  (
    .PAD(rst)
  );
  X_INV #(
    .LOC ( "IOB_X1Y58" ))
  \rst/IMUX  (
    .I(\rst/IBUF ),
    .O(rst_inv)
  );
  X_BUF #(
    .LOC ( "IOB_X1Y58" ))
  rst_IBUF (
    .I(rst),
    .O(\rst/IBUF )
  );
  X_IPAD #(
    .LOC ( "IOB_X1Y115" ))
  \ch1_to_rd_r<1>/PAD  (
    .PAD(ch1_to_rd_r[1])
  );
  X_BUF #(
    .LOC ( "IOB_X1Y115" ))
  ch1_to_rd_r_1_IBUF (
    .I(ch1_to_rd_r[1]),
    .O(\ch1_to_rd_r<1>/IBUF )
  );
  X_OPAD #(
    .LOC ( "IOB_X1Y46" ))
  \ch1_rd_i<13>/PAD  (
    .PAD(ch1_rd_i[13])
  );
  X_OBUF #(
    .LOC ( "IOB_X1Y46" ))
  ch1_rd_i_13_OBUF (
    .I(\ch1_to_rd_i<13>/IBUF ),
    .O(ch1_rd_i[13])
  );
  X_OPAD #(
    .LOC ( "IOB_X0Y56" ))
  \ch2_rd_i<10>/PAD  (
    .PAD(ch2_rd_i[10])
  );
  X_OBUF #(
    .LOC ( "IOB_X0Y56" ))
  ch2_rd_i_10_OBUF (
    .I(\ch2_to_rd_i<10>/IBUF ),
    .O(ch2_rd_i[10])
  );
  X_IPAD #(
    .LOC ( "IOB_X1Y109" ))
  \ch1_to_rd_r<2>/PAD  (
    .PAD(ch1_to_rd_r[2])
  );
  X_BUF #(
    .LOC ( "IOB_X1Y109" ))
  ch1_to_rd_r_2_IBUF (
    .I(ch1_to_rd_r[2]),
    .O(\ch1_to_rd_r<2>/IBUF )
  );
  X_OPAD #(
    .LOC ( "IOB_X0Y116" ))
  \ch1_rd_i<14>/PAD  (
    .PAD(ch1_rd_i[14])
  );
  X_OBUF #(
    .LOC ( "IOB_X0Y116" ))
  ch1_rd_i_14_OBUF (
    .I(\ch1_to_rd_i<14>/IBUF ),
    .O(ch1_rd_i[14])
  );
  X_OPAD #(
    .LOC ( "IOB_X0Y53" ))
  \ch2_rd_i<11>/PAD  (
    .PAD(ch2_rd_i[11])
  );
  X_OBUF #(
    .LOC ( "IOB_X0Y53" ))
  ch2_rd_i_11_OBUF (
    .I(\ch2_to_rd_i<11>/IBUF ),
    .O(ch2_rd_i[11])
  );
  X_IPAD #(
    .LOC ( "IOB_X1Y52" ))
  \ch1_to_rd_r<3>/PAD  (
    .PAD(ch1_to_rd_r[3])
  );
  X_BUF #(
    .LOC ( "IOB_X1Y52" ))
  ch1_to_rd_r_3_IBUF (
    .I(ch1_to_rd_r[3]),
    .O(\ch1_to_rd_r<3>/IBUF )
  );
  X_OPAD #(
    .LOC ( "IOB_X1Y51" ))
  \ch1_rd_i<15>/PAD  (
    .PAD(ch1_rd_i[15])
  );
  X_OBUF #(
    .LOC ( "IOB_X1Y51" ))
  ch1_rd_i_15_OBUF (
    .I(\ch1_to_rd_i<15>/IBUF ),
    .O(ch1_rd_i[15])
  );
  X_OPAD #(
    .LOC ( "IOB_X0Y91" ))
  \ch2_rd_i<12>/PAD  (
    .PAD(ch2_rd_i[12])
  );
  X_OBUF #(
    .LOC ( "IOB_X0Y91" ))
  ch2_rd_i_12_OBUF (
    .I(\ch2_to_rd_i<12>/IBUF ),
    .O(ch2_rd_i[12])
  );
  X_FF #(
    .LOC ( "SLICE_X6Y32" ),
    .INIT ( 1'b0 ))
  addr_rd_ch1_3 (
    .CE(VCC),
    .CLK(clk_BUFGP),
    .I(addr_rd_ch1_mux0000[3]),
    .O(addr_rd_ch1_3_952),
    .SET(GND),
    .RST(rst_inv)
  );
  X_LUT6 #(
    .LOC ( "SLICE_X6Y32" ),
    .INIT ( 64'hFE10FA50FA50FA50 ))
  \addr_rd_ch1_mux0000<3>1  (
    .ADR0(\Madd_addr_rd_ch2_addsub0001_lut<9>_0 ),
    .ADR1(\Madd_addr_rd_ch2_addsub0001_cy<8>_0 ),
    .ADR2(\addr_rd_ch1_add0002<3>_0 ),
    .ADR3(\addr_rd_ch1_addsub0001<3>_0 ),
    .ADR4(\Msub_addr_rd_ch1_addsub0000_lut<7>_0 ),
    .ADR5(N2),
    .O(addr_rd_ch1_mux0000[3])
  );
  X_FF #(
    .LOC ( "SLICE_X6Y32" ),
    .INIT ( 1'b0 ))
  addr_rd_ch1_2 (
    .CE(VCC),
    .CLK(clk_BUFGP),
    .I(addr_rd_ch1_mux0000[2]),
    .O(addr_rd_ch1_2_951),
    .SET(GND),
    .RST(rst_inv)
  );
  X_LUT6 #(
    .LOC ( "SLICE_X6Y32" ),
    .INIT ( 64'hFE10FA50FA50FA50 ))
  \addr_rd_ch1_mux0000<2>1  (
    .ADR0(\Madd_addr_rd_ch2_addsub0001_lut<9>_0 ),
    .ADR1(\Madd_addr_rd_ch2_addsub0001_cy<8>_0 ),
    .ADR2(\addr_rd_ch1_add0002<2>_0 ),
    .ADR3(\addr_rd_ch1_addsub0001<2>_0 ),
    .ADR4(\Msub_addr_rd_ch1_addsub0000_lut<7>_0 ),
    .ADR5(N2),
    .O(addr_rd_ch1_mux0000[2])
  );
  X_FF #(
    .LOC ( "SLICE_X6Y32" ),
    .INIT ( 1'b0 ))
  addr_rd_ch1_1 (
    .CE(VCC),
    .CLK(clk_BUFGP),
    .I(addr_rd_ch1_mux0000[1]),
    .O(addr_rd_ch1_1_950),
    .SET(GND),
    .RST(rst_inv)
  );
  X_LUT6 #(
    .LOC ( "SLICE_X6Y32" ),
    .INIT ( 64'hFE10FA50FA50FA50 ))
  \addr_rd_ch1_mux0000<1>1  (
    .ADR0(\Madd_addr_rd_ch2_addsub0001_lut<9>_0 ),
    .ADR1(\Madd_addr_rd_ch2_addsub0001_cy<8>_0 ),
    .ADR2(\addr_rd_ch1_add0002<1>_0 ),
    .ADR3(\addr_rd_ch1_addsub0001<1>_0 ),
    .ADR4(\Msub_addr_rd_ch1_addsub0000_lut<7>_0 ),
    .ADR5(N2),
    .O(addr_rd_ch1_mux0000[1])
  );
  X_FF #(
    .LOC ( "SLICE_X6Y32" ),
    .INIT ( 1'b0 ))
  addr_rd_ch1_0 (
    .CE(VCC),
    .CLK(clk_BUFGP),
    .I(addr_rd_ch1_mux0000[0]),
    .O(addr_rd_ch1_0_949),
    .SET(GND),
    .RST(rst_inv)
  );
  X_LUT6 #(
    .LOC ( "SLICE_X6Y32" ),
    .INIT ( 64'hFE10FA50FA50FA50 ))
  \addr_rd_ch1_mux0000<0>1  (
    .ADR0(\Madd_addr_rd_ch2_addsub0001_lut<9>_0 ),
    .ADR1(\Madd_addr_rd_ch2_addsub0001_cy<8>_0 ),
    .ADR2(\addr_rd_ch1_add0002<0>_0 ),
    .ADR3(\addr_rd_ch1_addsub0001<0>_0 ),
    .ADR4(\Msub_addr_rd_ch1_addsub0000_lut<7>_0 ),
    .ADR5(N2),
    .O(addr_rd_ch1_mux0000[0])
  );
  X_FF #(
    .LOC ( "SLICE_X6Y38" ),
    .INIT ( 1'b0 ))
  addr_rd_ch2_8 (
    .CE(VCC),
    .CLK(clk_BUFGP),
    .I(addr_rd_ch2_mux0000[8]),
    .O(addr_rd_ch2_8_973),
    .SET(GND),
    .RST(rst_inv)
  );
  X_LUT6 #(
    .LOC ( "SLICE_X6Y38" ),
    .INIT ( 64'hFCFC00000203AAFF ))
  \addr_rd_ch2_mux0000<8>1  (
    .ADR0(\Madd_addr_rd_ch2_addsub0001_lut<9>_0 ),
    .ADR1(\Msub_addr_rd_ch1_addsub0000_cy<5>_0 ),
    .ADR2(\addr_rd_ch1_addsub0001<6>_0 ),
    .ADR3(\addr_rd_ch1_add0002<8>_0 ),
    .ADR4(\Msub_addr_rd_ch1_addsub0000_lut<7>_0 ),
    .ADR5(\Madd_addr_rd_ch2_addsub0001_cy<8>_0 ),
    .O(addr_rd_ch2_mux0000[8])
  );
  X_FF #(
    .LOC ( "SLICE_X6Y38" ),
    .INIT ( 1'b0 ))
  addr_rd_ch2_7 (
    .CE(VCC),
    .CLK(clk_BUFGP),
    .I(addr_rd_ch2_mux0000[7]),
    .O(addr_rd_ch2_7_971),
    .SET(GND),
    .RST(rst_inv)
  );
  X_LUT6 #(
    .LOC ( "SLICE_X6Y38" ),
    .INIT ( 64'h0033FFCC0032FAD8 ))
  \addr_rd_ch2_mux0000<7>1  (
    .ADR0(\Madd_addr_rd_ch2_addsub0001_lut<9>_0 ),
    .ADR1(\Msub_addr_rd_ch1_addsub0000_cy<5>_0 ),
    .ADR2(\addr_rd_ch1_add0002<7>_0 ),
    .ADR3(\addr_rd_ch1_addsub0001<6>_0 ),
    .ADR4(\Msub_addr_rd_ch1_addsub0000_lut<7>_0 ),
    .ADR5(\Madd_addr_rd_ch2_addsub0001_cy<8>_0 ),
    .O(addr_rd_ch2_mux0000[7])
  );
  X_FF #(
    .LOC ( "SLICE_X6Y39" ),
    .INIT ( 1'b0 ))
  addr_rd_ch1_7 (
    .CE(VCC),
    .CLK(clk_BUFGP),
    .I(addr_rd_ch1_mux0000[7]),
    .O(addr_rd_ch1_7_961),
    .SET(GND),
    .RST(rst_inv)
  );
  X_LUT6 #(
    .LOC ( "SLICE_X6Y39" ),
    .INIT ( 64'h0032FAD85072FAD8 ))
  \addr_rd_ch1_mux0000<7>1  (
    .ADR0(\Madd_addr_rd_ch2_addsub0001_lut<9>_0 ),
    .ADR1(\Msub_addr_rd_ch1_addsub0000_cy<5>_0 ),
    .ADR2(\addr_rd_ch1_add0002<7>_0 ),
    .ADR3(\addr_rd_ch1_addsub0001<6>_0 ),
    .ADR4(\Msub_addr_rd_ch1_addsub0000_lut<7>_0 ),
    .ADR5(\Madd_addr_rd_ch2_addsub0001_cy<8>_0 ),
    .O(addr_rd_ch1_mux0000[7])
  );
  X_FF #(
    .LOC ( "SLICE_X6Y39" ),
    .INIT ( 1'b0 ))
  addr_rd_ch1_6 (
    .CE(VCC),
    .CLK(clk_BUFGP),
    .I(addr_rd_ch1_mux0000[6]),
    .O(addr_rd_ch1_6_958),
    .SET(GND),
    .RST(rst_inv)
  );
  X_LUT6 #(
    .LOC ( "SLICE_X6Y39" ),
    .INIT ( 64'hF00EE44EE44EE44E ))
  \addr_rd_ch1_mux0000<6>1  (
    .ADR0(\Madd_addr_rd_ch2_addsub0001_lut<9>_0 ),
    .ADR1(\addr_rd_ch1_add0002<6>_0 ),
    .ADR2(\Msub_addr_rd_ch1_addsub0000_cy<5>_0 ),
    .ADR3(\addr_rd_ch1_addsub0001<6>_0 ),
    .ADR4(\Msub_addr_rd_ch1_addsub0000_lut<7>_0 ),
    .ADR5(\Madd_addr_rd_ch2_addsub0001_cy<8>_0 ),
    .O(addr_rd_ch1_mux0000[6])
  );
  X_FF #(
    .LOC ( "SLICE_X6Y39" ),
    .INIT ( 1'b0 ))
  addr_rd_ch1_5 (
    .CE(VCC),
    .CLK(clk_BUFGP),
    .I(addr_rd_ch1_mux0000[5]),
    .O(addr_rd_ch1_5_956),
    .SET(GND),
    .RST(rst_inv)
  );
  X_LUT6 #(
    .LOC ( "SLICE_X6Y39" ),
    .INIT ( 64'h0F0E4E4E4E4E4E4E ))
  \addr_rd_ch1_mux0000<5>1  (
    .ADR0(\Madd_addr_rd_ch2_addsub0001_lut<9>_0 ),
    .ADR1(\addr_rd_ch1_add0002<5>_0 ),
    .ADR2(\Msub_addr_rd_ch1_addsub0000_cy<5>_0 ),
    .ADR3(\addr_rd_ch1_addsub0001<6>_0 ),
    .ADR4(\Msub_addr_rd_ch1_addsub0000_lut<7>_0 ),
    .ADR5(\Madd_addr_rd_ch2_addsub0001_cy<8>_0 ),
    .O(addr_rd_ch1_mux0000[5])
  );
  X_FF #(
    .LOC ( "SLICE_X6Y39" ),
    .INIT ( 1'b0 ))
  addr_rd_ch1_4 (
    .CE(VCC),
    .CLK(clk_BUFGP),
    .I(addr_rd_ch1_mux0000[4]),
    .O(addr_rd_ch1_4_954),
    .SET(GND),
    .RST(rst_inv)
  );
  X_LUT6 #(
    .LOC ( "SLICE_X6Y39" ),
    .INIT ( 64'hFE10FA50FA50FA50 ))
  \addr_rd_ch1_mux0000<4>1  (
    .ADR0(\Madd_addr_rd_ch2_addsub0001_lut<9>_0 ),
    .ADR1(\Madd_addr_rd_ch2_addsub0001_cy<8>_0 ),
    .ADR2(\addr_rd_ch1_add0002<4>_0 ),
    .ADR3(\addr_rd_ch1_addsub0001<4>_0 ),
    .ADR4(\Msub_addr_rd_ch1_addsub0000_lut<7>_0 ),
    .ADR5(N2),
    .O(addr_rd_ch1_mux0000[4])
  );
  X_FF #(
    .LOC ( "SLICE_X7Y32" ),
    .INIT ( 1'b0 ))
  addr_rd_ch2_3 (
    .CE(VCC),
    .CLK(clk_BUFGP),
    .I(addr_rd_ch2_mux0000[3]),
    .O(addr_rd_ch2_3_960),
    .SET(GND),
    .RST(rst_inv)
  );
  X_LUT6 #(
    .LOC ( "SLICE_X7Y32" ),
    .INIT ( 64'hAAABAAA8ABABA8A8 ))
  \addr_rd_ch2_mux0000<3>  (
    .ADR0(\addr_rd_ch1_addsub0001<3>_0 ),
    .ADR1(\Madd_addr_rd_ch2_addsub0001_lut<9>_0 ),
    .ADR2(\Madd_addr_rd_ch2_addsub0001_cy<8>_0 ),
    .ADR3(\Msub_addr_rd_ch1_addsub0000_lut<7>_0 ),
    .ADR4(\addr_rd_ch1_add0002<3>_0 ),
    .ADR5(N2),
    .O(addr_rd_ch2_mux0000[3])
  );
  X_FF #(
    .LOC ( "SLICE_X7Y32" ),
    .INIT ( 1'b0 ))
  addr_rd_ch2_2 (
    .CE(VCC),
    .CLK(clk_BUFGP),
    .I(addr_rd_ch2_mux0000[2]),
    .O(addr_rd_ch2_2_957),
    .SET(GND),
    .RST(rst_inv)
  );
  X_LUT6 #(
    .LOC ( "SLICE_X7Y32" ),
    .INIT ( 64'hAAABAAA8ABABA8A8 ))
  \addr_rd_ch2_mux0000<2>  (
    .ADR0(\addr_rd_ch1_addsub0001<2>_0 ),
    .ADR1(\Madd_addr_rd_ch2_addsub0001_lut<9>_0 ),
    .ADR2(\Madd_addr_rd_ch2_addsub0001_cy<8>_0 ),
    .ADR3(\Msub_addr_rd_ch1_addsub0000_lut<7>_0 ),
    .ADR4(\addr_rd_ch1_add0002<2>_0 ),
    .ADR5(N2),
    .O(addr_rd_ch2_mux0000[2])
  );
  X_FF #(
    .LOC ( "SLICE_X7Y32" ),
    .INIT ( 1'b0 ))
  addr_rd_ch2_1 (
    .CE(VCC),
    .CLK(clk_BUFGP),
    .I(addr_rd_ch2_mux0000[1]),
    .O(addr_rd_ch2_1_955),
    .SET(GND),
    .RST(rst_inv)
  );
  X_LUT6 #(
    .LOC ( "SLICE_X7Y32" ),
    .INIT ( 64'hAAABAAA8ABABA8A8 ))
  \addr_rd_ch2_mux0000<1>  (
    .ADR0(\addr_rd_ch1_addsub0001<1>_0 ),
    .ADR1(\Madd_addr_rd_ch2_addsub0001_lut<9>_0 ),
    .ADR2(\Madd_addr_rd_ch2_addsub0001_cy<8>_0 ),
    .ADR3(\Msub_addr_rd_ch1_addsub0000_lut<7>_0 ),
    .ADR4(\addr_rd_ch1_add0002<1>_0 ),
    .ADR5(N2),
    .O(addr_rd_ch2_mux0000[1])
  );
  X_FF #(
    .LOC ( "SLICE_X7Y32" ),
    .INIT ( 1'b0 ))
  addr_rd_ch2_0 (
    .CE(VCC),
    .CLK(clk_BUFGP),
    .I(addr_rd_ch2_mux0000[0]),
    .O(addr_rd_ch2_0_953),
    .SET(GND),
    .RST(rst_inv)
  );
  X_LUT6 #(
    .LOC ( "SLICE_X7Y32" ),
    .INIT ( 64'hAAABAAA8ABABA8A8 ))
  \addr_rd_ch2_mux0000<0>  (
    .ADR0(\addr_rd_ch1_addsub0001<0>_0 ),
    .ADR1(\Madd_addr_rd_ch2_addsub0001_lut<9>_0 ),
    .ADR2(\Madd_addr_rd_ch2_addsub0001_cy<8>_0 ),
    .ADR3(\Msub_addr_rd_ch1_addsub0000_lut<7>_0 ),
    .ADR4(\addr_rd_ch1_add0002<0>_0 ),
    .ADR5(N2),
    .O(addr_rd_ch2_mux0000[0])
  );
  X_FF #(
    .LOC ( "SLICE_X7Y37" ),
    .INIT ( 1'b0 ))
  addr_rd_ch1_8 (
    .CE(VCC),
    .CLK(clk_BUFGP),
    .I(addr_rd_ch1_mux0000[8]),
    .O(addr_rd_ch1_8_964),
    .SET(GND),
    .RST(rst_inv)
  );
  X_LUT6 #(
    .LOC ( "SLICE_X7Y37" ),
    .INIT ( 64'h0302FFAAFDA85500 ))
  \addr_rd_ch1_mux0000<8>1  (
    .ADR0(\Madd_addr_rd_ch2_addsub0001_lut<9>_0 ),
    .ADR1(\Msub_addr_rd_ch1_addsub0000_cy<5>_0 ),
    .ADR2(\addr_rd_ch1_addsub0001<6>_0 ),
    .ADR3(\addr_rd_ch1_add0002<8>_0 ),
    .ADR4(\Msub_addr_rd_ch1_addsub0000_lut<7>_0 ),
    .ADR5(\Madd_addr_rd_ch2_addsub0001_cy<8>_0 ),
    .O(addr_rd_ch1_mux0000[8])
  );
  X_FF #(
    .LOC ( "SLICE_X7Y39" ),
    .INIT ( 1'b0 ))
  addr_rd_ch2_6 (
    .CE(VCC),
    .CLK(clk_BUFGP),
    .I(addr_rd_ch2_mux0000[6]),
    .O(addr_rd_ch2_6_969),
    .SET(GND),
    .RST(rst_inv)
  );
  X_LUT6 #(
    .LOC ( "SLICE_X7Y39" ),
    .INIT ( 64'hF00FF00FF00EE44E ))
  \addr_rd_ch2_mux0000<6>1  (
    .ADR0(\Madd_addr_rd_ch2_addsub0001_lut<9>_0 ),
    .ADR1(\addr_rd_ch1_add0002<6>_0 ),
    .ADR2(\Msub_addr_rd_ch1_addsub0000_cy<5>_0 ),
    .ADR3(\addr_rd_ch1_addsub0001<6>_0 ),
    .ADR4(\Msub_addr_rd_ch1_addsub0000_lut<7>_0 ),
    .ADR5(\Madd_addr_rd_ch2_addsub0001_cy<8>_0 ),
    .O(addr_rd_ch2_mux0000[6])
  );
  X_FF #(
    .LOC ( "SLICE_X7Y39" ),
    .INIT ( 1'b0 ))
  addr_rd_ch2_5 (
    .CE(VCC),
    .CLK(clk_BUFGP),
    .I(addr_rd_ch2_mux0000[5]),
    .O(addr_rd_ch2_5_966),
    .SET(GND),
    .RST(rst_inv)
  );
  X_LUT6 #(
    .LOC ( "SLICE_X7Y39" ),
    .INIT ( 64'h0F0F0F0F0F0E4E4E ))
  \addr_rd_ch2_mux0000<5>1  (
    .ADR0(\Madd_addr_rd_ch2_addsub0001_lut<9>_0 ),
    .ADR1(\addr_rd_ch1_add0002<5>_0 ),
    .ADR2(\Msub_addr_rd_ch1_addsub0000_cy<5>_0 ),
    .ADR3(\addr_rd_ch1_addsub0001<6>_0 ),
    .ADR4(\Msub_addr_rd_ch1_addsub0000_lut<7>_0 ),
    .ADR5(\Madd_addr_rd_ch2_addsub0001_cy<8>_0 ),
    .O(addr_rd_ch2_mux0000[5])
  );
  X_LUT6 #(
    .LOC ( "SLICE_X7Y39" ),
    .INIT ( 64'hFFFFFFFFFFFF0000 ))
  \addr_rd_ch2_mux0000<4>_SW0  (
    .ADR0(1'b1),
    .ADR1(1'b1),
    .ADR2(1'b1),
    .ADR3(1'b1),
    .ADR4(\Msub_addr_rd_ch1_addsub0000_cy<5>_0 ),
    .ADR5(\addr_rd_ch1_addsub0001<6>_0 ),
    .O(N2)
  );
  X_FF #(
    .LOC ( "SLICE_X7Y39" ),
    .INIT ( 1'b0 ))
  addr_rd_ch2_4 (
    .CE(VCC),
    .CLK(clk_BUFGP),
    .I(addr_rd_ch2_mux0000[4]),
    .O(addr_rd_ch2_4_963),
    .SET(GND),
    .RST(rst_inv)
  );
  X_LUT6 #(
    .LOC ( "SLICE_X7Y39" ),
    .INIT ( 64'hAAABAAA8ABABA8A8 ))
  \addr_rd_ch2_mux0000<4>  (
    .ADR0(\addr_rd_ch1_addsub0001<4>_0 ),
    .ADR1(\Madd_addr_rd_ch2_addsub0001_lut<9>_0 ),
    .ADR2(\Madd_addr_rd_ch2_addsub0001_cy<8>_0 ),
    .ADR3(\Msub_addr_rd_ch1_addsub0000_lut<7>_0 ),
    .ADR4(\addr_rd_ch1_add0002<4>_0 ),
    .ADR5(N2),
    .O(addr_rd_ch2_mux0000[4])
  );
  X_LUT6 #(
    .LOC ( "SLICE_X19Y34" ),
    .INIT ( 64'hFFFF000000000000 ))
  count_cmp_eq0000_SW1 (
    .ADR0(1'b1),
    .ADR1(1'b1),
    .ADR2(1'b1),
    .ADR3(1'b1),
    .ADR4(count[3]),
    .ADR5(count[4]),
    .O(N22)
  );
  X_LUT6 #(
    .LOC ( "SLICE_X19Y35" ),
    .INIT ( 64'hFFFFFFFF7FFFFFFF ))
  count_cmp_eq0000_inv1 (
    .ADR0(count[4]),
    .ADR1(count[3]),
    .ADR2(count[2]),
    .ADR3(count[1]),
    .ADR4(count[0]),
    .ADR5(N01),
    .O(count_cmp_eq0000_inv)
  );
  X_LUT6 #(
    .LOC ( "SLICE_X19Y35" ),
    .INIT ( 64'hFFFFFFFFFFFFF0FF ))
  count_cmp_eq0000_SW0 (
    .ADR0(1'b1),
    .ADR1(1'b1),
    .ADR2(count[6]),
    .ADR3(count[7]),
    .ADR4(count[5]),
    .ADR5(count[8]),
    .O(N01)
  );
  X_LUT6 #(
    .LOC ( "SLICE_X19Y35" ),
    .INIT ( 64'hFFFF00007FFF0000 ))
  \Mcount_count_lut<0>  (
    .ADR0(count[4]),
    .ADR1(count[3]),
    .ADR2(count[2]),
    .ADR3(count[1]),
    .ADR4(count[0]),
    .ADR5(N01),
    .O(\Mcount_count_lut[0] )
  );
  X_CKBUF #(
    .LOC ( "BUFGCTRL_X0Y0" ))
  \clk_BUFGP/BUFG/BUF  (
    .I(\clk/IBUF ),
    .O(clk_BUFGP)
  );
  X_ONE   NlwBlock_MEM_RD_DUAL_VCC (
    .O(VCC)
  );
  X_ZERO   NlwBlock_MEM_RD_DUAL_GND (
    .O(GND)
  );
endmodule


`ifndef GLBL
`define GLBL

`timescale  1 ps / 1 ps

module glbl ();

    parameter ROC_WIDTH = 100000;
    parameter TOC_WIDTH = 0;

//--------   STARTUP Globals --------------
    wire GSR;
    wire GTS;
    wire GWE;
    wire PRLD;
    tri1 p_up_tmp;
    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;

    wire PROGB_GLBL;
    wire CCLKO_GLBL;

    reg GSR_int;
    reg GTS_int;
    reg PRLD_int;

//--------   JTAG Globals --------------
    wire JTAG_TDO_GLBL;
    wire JTAG_TCK_GLBL;
    wire JTAG_TDI_GLBL;
    wire JTAG_TMS_GLBL;
    wire JTAG_TRST_GLBL;

    reg JTAG_CAPTURE_GLBL;
    reg JTAG_RESET_GLBL;
    reg JTAG_SHIFT_GLBL;
    reg JTAG_UPDATE_GLBL;
    reg JTAG_RUNTEST_GLBL;

    reg JTAG_SEL1_GLBL = 0;
    reg JTAG_SEL2_GLBL = 0 ;
    reg JTAG_SEL3_GLBL = 0;
    reg JTAG_SEL4_GLBL = 0;

    reg JTAG_USER_TDO1_GLBL = 1'bz;
    reg JTAG_USER_TDO2_GLBL = 1'bz;
    reg JTAG_USER_TDO3_GLBL = 1'bz;
    reg JTAG_USER_TDO4_GLBL = 1'bz;

    assign (weak1, weak0) GSR = GSR_int;
    assign (weak1, weak0) GTS = GTS_int;
    assign (weak1, weak0) PRLD = PRLD_int;

    initial begin
	GSR_int = 1'b1;
	PRLD_int = 1'b1;
	#(ROC_WIDTH)
	GSR_int = 1'b0;
	PRLD_int = 1'b0;
    end

    initial begin
	GTS_int = 1'b1;
	#(TOC_WIDTH)
	GTS_int = 1'b0;
    end

endmodule

`endif

